CSBGEN - Command Stream Buffer Generator

CSBGEN is a code generator for pack/unpack functions used by the Imagination PowerVR GPU drivers. It generates C structures and functions from XML descriptions of hardware registers and command buffers.

The generator parses XML files that describe the hardware interface and generates:

  • C structures matching hardware register layouts

  • Pack functions to convert from C structures to raw binary data for GPU

  • Unpack functions to convert from raw binary data back to C structures

  • Helper macros and default values for fields

Hardware Interfaces

CSBGEN generates code for the following PowerVR Rogue hardware interfaces:

  • CDM (Compute Data Master) - Compute control stream

  • CR (Control Registers)

  • IPF (Internal Parameter Format)

  • LLS (Low-Latency Scheduling)

  • PBESTATE (Pixel Backend State)

  • PDS (Programmable Data Sequencer)

  • PPP (Primitive Processing Pipeline)

  • TEXSTATE (Texture State)

  • VDM (Vertex Data Master) - Geometry control stream

CDM (Compute Data Master)

Complete API documentation for CDM control stream structures and functions:

ROGUE_CDMCTRL_GUARD_SIZE_DEFAULT

The driver must not put any STREAM_LINK or STREAM_TERMINATE blocks in the final GUARD_SIZE bytes of the last valid page.

enum ROGUE_CDMCTRL_BLOCK_TYPE

The CDM control stream block header type.

enumerator ROGUE_CDMCTRL_BLOCK_TYPE_COMPUTE_KERNEL = 0

Compute Kernel.

Stream Link.

enumerator ROGUE_CDMCTRL_BLOCK_TYPE_STREAM_TERMINATE = 2

Stream Terminate.

ROGUE_CDMCTRL_KERNEL0_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL0

ROGUE_CDMCTRL_KERNEL1_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL1

ROGUE_CDMCTRL_KERNEL2_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL2

ROGUE_CDMCTRL_KERNEL3_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL3

ROGUE_CDMCTRL_KERNEL4_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL4

ROGUE_CDMCTRL_KERNEL5_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL5

ROGUE_CDMCTRL_KERNEL6_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL6

ROGUE_CDMCTRL_KERNEL7_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL7

ROGUE_CDMCTRL_KERNEL8_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL8

ROGUE_CDMCTRL_KERNEL9_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL9

ROGUE_CDMCTRL_KERNEL10_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL10

ROGUE_CDMCTRL_KERNEL11_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_KERNEL11

ROGUE_CDMCTRL_STREAM_LINK0_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_STREAM_LINK0

struct ROGUE_CDMCTRL_STREAM_LINK0

Stream Link.

enum ROGUE_CDMCTRL_BLOCK_TYPE block_type

Stream Link header.

Bits: [30:31] Default: STREAM_LINK

MSB of Stream link address.

Bits: [0:7]

ROGUE_CDMCTRL_STREAM_LINK1_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_STREAM_LINK1

ROGUE_CDMCTRL_STREAM_TERMINATE_length

Number of 32-bit words used to encode ROGUE_CDMCTRL_STREAM_TERMINATE

struct ROGUE_CDMCTRL_STREAM_TERMINATE

CDM Stream Terminate.

enum ROGUE_CDMCTRL_BLOCK_TYPE block_type

Bits: [30:31] Default: STREAM_TERMINATE

CR (Control Registers)

API documentation for Control Register structures and functions:

ROGUE_CR_PM_VHEAP_TABLE_SIZE

Size of the PM virtual heap table in DWords.

enum ROGUE_CR_COMP_IADDR_TYPE

Compressor indirect addressing mode.

enum ROGUE_CR_COMPRESS_SIZE

Compressor block size extension bit.

enum ROGUE_CR_MEMLAYOUT

Sets the memory layout.

enum ROGUE_CR_ROTATION_TYPE

Sets the rotation.

enum ROGUE_CR_SIZE

Size of twiddled render in pixel units.

enum ROGUE_CR_SWIZ

Sets the swizzle.

enumerator ROGUE_CR_SWIZ_SOURCE_CHAN0 = 0

Indicates source channel0 goes to this destination channel.

enumerator ROGUE_CR_SWIZ_SOURCE_CHAN1 = 1

Indicates source channel1 goes to this destination channel.

enumerator ROGUE_CR_SWIZ_SOURCE_CHAN2 = 2

Indicates source channel2 goes to this destination channel.

enumerator ROGUE_CR_SWIZ_SOURCE_CHAN3 = 3

Indicates source channel3 goes to this destination channel.

enumerator ROGUE_CR_SWIZ_ONE = 4

Send a value of 1 to this destination channel.

enumerator ROGUE_CR_SWIZ_ZERO = 5

Send a value of 0 to this destination channel.

enum ROGUE_CR_TFBC_LOSSY

Sets the lossy bit for frame buffer compression.

enum ROGUE_CR_TWOCOMP_GAMMA

Sets the gamma mode for 2 component textures.

ROGUE_CR_PM_MTILE_ARRAY_length

Number of 32-bit words used to encode ROGUE_CR_PM_MTILE_ARRAY

struct ROGUE_CR_PM_MTILE_ARRAY

Effective immediately.

uint64_t base_addr

1TB Addressable, 128-bits aligned Base Address for Mtile Array Base.

Bits: [4:39]

ROGUE_CR_PM_VHEAP_TABLE_length

Number of 32-bit words used to encode ROGUE_CR_PM_VHEAP_TABLE

struct ROGUE_CR_PM_VHEAP_TABLE

Effective immediately, this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE DWords.

uint64_t base_addr

1TB Addressable, 128-bits aligned Base Address for Virtual Heap Table.

Bits: [4:39]

ROGUE_CR_PM_MLIST0_BASE_length

Number of 32-bit words used to encode ROGUE_CR_PM_MLIST0_BASE

struct ROGUE_CR_PM_MLIST0_BASE

This register defines the base address of the MMU list 0 for the MMU pages, the stride has to be 64KBytes.

uint64_t addr

1TB Addressable, 128-bits aligned Base Address for MMU list0 module. Effective immediately.

Bits: [4:39]

ROGUE_CR_VDM_CTRL_STREAM_BASE_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CTRL_STREAM_BASE

struct ROGUE_CR_VDM_CTRL_STREAM_BASE

The base address of the Vertex Data Master’s Input Parameter Control Stream in external memory.

uint64_t addr

1TB range, 32-bit aligned base address.

Bits: [2:39]

ROGUE_CR_VDM_CALL_STACK_POINTER_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CALL_STACK_POINTER

struct ROGUE_CR_VDM_CALL_STACK_POINTER

The pointer to the control stream call stack.

The current pointer within the VDM’s call stack in external memory. The call stack is used whenever a call is made to another control stream, to store the return address (location in current control stream). This register should be programmed before each TA which uses a call stack. This register needs to be saved/restored for each context.

uint64_t addr

1TB range, 64-bit aligned base address.

Bits: [3:39]

ROGUE_CR_VDM_CONTEXT_STATE_BASE_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_STATE_BASE

struct ROGUE_CR_VDM_CONTEXT_STATE_BASE

The base address in external memory of the VDM’s context state buffer. On a context store the VDM will store its state to this address, and reload it on a context resume. The size and format of the data written is defined in the LLS section of the TRM. This register must be programmed before initiating a context store by writing to VDM_CONTEXT_STORE_START_PULSE.

uint64_t addr

1TB range, 128-bit aligned base address.

Bits: [4:39]

ROGUE_CR_VDM_CONTEXT_STORE_TASK0_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_STORE_TASK0

struct ROGUE_CR_VDM_CONTEXT_STORE_TASK0

These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t pds_state1

Bits: [32:63]

uint32_t pds_state0

Bits: [0:31]

ROGUE_CR_VDM_CONTEXT_STORE_TASK1_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_STORE_TASK1

struct ROGUE_CR_VDM_CONTEXT_STORE_TASK1

This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t pds_state2

Bits: [0:31]

ROGUE_CR_VDM_CONTEXT_STORE_TASK2_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_STORE_TASK2

struct ROGUE_CR_VDM_CONTEXT_STORE_TASK2

These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t stream_out2

Bits: [32:63]

uint32_t stream_out1

Bits: [0:31]

ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_RESUME_TASK0

struct ROGUE_CR_VDM_CONTEXT_RESUME_TASK0

These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t pds_state1

Bits: [32:63]

uint32_t pds_state0

Bits: [0:31]

ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_RESUME_TASK1

struct ROGUE_CR_VDM_CONTEXT_RESUME_TASK1

This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t pds_state2

Bits: [0:31]

ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_length

Number of 32-bit words used to encode ROGUE_CR_VDM_CONTEXT_RESUME_TASK2

struct ROGUE_CR_VDM_CONTEXT_RESUME_TASK2

These words defines the Stream Out Sync program which will be written, as a PPP State Update, by the VDM to its context resume control stream on a context store operation. This register must be programmed before writing to VDM_CONTEXT_STORE_START_PULSE.

uint32_t stream_out2

Bits: [32:63]

uint32_t stream_out1

Bits: [0:31]

ROGUE_CR_CDM_CONTEXT_STATE_BASE_length

Number of 32-bit words used to encode ROGUE_CR_CDM_CONTEXT_STATE_BASE

struct ROGUE_CR_CDM_CONTEXT_STATE_BASE

The base address in external memory of the CDM’s context state buffer, to which it will store its snapshot state on a context store and from which it will reload on a context resume.

uint64_t addr

1TB range, 128-bit aligned base address.

Bits: [4:39]

ROGUE_CR_CDM_CONTEXT_PDS0_length

Number of 32-bit words used to encode ROGUE_CR_CDM_CONTEXT_PDS0

struct ROGUE_CR_CDM_CONTEXT_PDS0

This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load.

uint64_t data_addr

PDS Data Address for Store/Load Program, 128-bit aligned.

Bits: [36:63]

uint64_t code_addr

PDS Code Address for Store/Load Program, 128-bit aligned.

Bits: [4:31]

ROGUE_CR_CDM_CTRL_STREAM_BASE_length

Number of 32-bit words used to encode ROGUE_CR_CDM_CTRL_STREAM_BASE

struct ROGUE_CR_CDM_CTRL_STREAM_BASE

The base address of the Compute Data Master’s Input Parameter Control Stream in external memory.

uint64_t addr

1TB range, 32-bit aligned base address.

Bits: [2:39]

ROGUE_CR_CDM_CONTEXT_PDS1_length

Number of 32-bit words used to encode ROGUE_CR_CDM_CONTEXT_PDS1

struct ROGUE_CR_CDM_CONTEXT_PDS1

This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS.

bool pds_seq_dep

PDS Sequential Dependency.

Bits: [29:29]

bool usc_seq_dep

USC Sequential Dependency.

Bits: [28:28]

bool target

USC Target (0=All, 1=Any).

Bits: [27:27]

uint32_t unified_size

Unified Size.

Bits: [21:26]

bool common_shared

PDS Common Store Allocation is Shared Registers.

Bits: [20:20]

uint32_t common_size

PDS Common Size.

Bits: [11:19]

uint32_t temp_size

PDS Temp Size.

Bits: [7:10]

uint32_t data_size

PDS Data Size.

Bits: [1:6]

bool fence

Fence the Task in the PDS/USC - Set on Store, unset on Load.

Bits: [0:0]

ROGUE_CR_CDM_TERMINATE_PDS_length

Number of 32-bit words used to encode ROGUE_CR_CDM_TERMINATE_PDS

struct ROGUE_CR_CDM_TERMINATE_PDS

This register contains the PDS Code and Data Addresses for the Terminate Program. This program is sent to PDS on Context Store after the Context Store Program.

uint64_t data_addr

PDS Data Address for Terminate Program, 128-bit aligned.

Bits: [36:63]

uint64_t code_addr

PDS Code Address for Terminate Program, 128-bit aligned.

Bits: [4:31]

ROGUE_CR_CDM_TERMINATE_PDS1_length

Number of 32-bit words used to encode ROGUE_CR_CDM_TERMINATE_PDS1

struct ROGUE_CR_CDM_TERMINATE_PDS1

This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS.

bool pds_seq_dep

PDS Sequential Dependency.

Bits: [29:29]

bool usc_seq_dep

USC Sequential Dependency.

Bits: [28:28]

bool target

USC Target (0=All, 1=Any).

Bits: [27:27]

uint32_t unified_size

Unified Size.

Bits: [21:26]

bool common_shared

PDS Common Store Allocation is Shared Registers.

Bits: [20:20]

uint32_t common_size

PDS Common Size.

Bits: [11:19]

uint32_t temp_size

PDS Temp Size.

Bits: [7:10]

uint32_t data_size

PDS Data Size.

Bits: [1:6]

bool fence

Fence the Task in the PDS/USC - Set on Store Terminate.

Bits: [0:0]

ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_length

Number of 32-bit words used to encode ROGUE_CR_CDM_CONTEXT_LOAD_PDS0

struct ROGUE_CR_CDM_CONTEXT_LOAD_PDS0

This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load.

uint64_t data_addr

PDS Data Address for Store/Load Program, 128-bit aligned.

Bits: [36:63]

uint64_t code_addr

PDS Code Address for Store/Load Program, 128-bit aligned.

Bits: [4:31]

ROGUE_CR_COMPUTE_CLUSTER_length

Number of 32-bit words used to encode ROGUE_CR_COMPUTE_CLUSTER

struct ROGUE_CR_COMPUTE_CLUSTER

This mask register enables CDM output to the Clusters present in the design. Resets to a single Cluster being driven with Compute Tasks. To enable Compute processing on more USCs, write this register appropriately.

The register should only be programmed with a marching 1’s pattern; for example in a 4 Cluster configuration the following values are valid:

0x1 - USC0 will process Compute Tasks 0x3 - USC0,1 will process Compute Tasks 0x7 - USC0,1,2 will process Compute Tasks 0xF - USC0,1,2,3 will process Compute Tasks

If the system contains more than 4 Clusters, then higher values are valid to enable Compute processing on those Clusters.

uint32_t mask

A Mask of Clusters enabled for Compute processing. 1 = USC0 only, 3 = USC0 and 1, 7=USC0,1,2 and 3 etc.

Bits: [0:31]

ROGUE_CR_CDM_ITEM_length

Number of 32-bit words used to encode ROGUE_CR_CDM_ITEM

struct ROGUE_CR_CDM_ITEM

This register defines the order in which the CDM will output Work Items within a Work group.

enum ROGUE_CR_CDM_ITEM_MODE mode

Bits: [0:1]

ROGUE_CR_PDS_CTRL_length

Number of 32-bit words used to encode ROGUE_CR_PDS_CTRL

struct ROGUE_CR_PDS_CTRL

Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system.

bool sm_overlap_enable

Enable per Data Master slot tracking within the PDS Slot Manager (SM) for improved performance while running overlapped.

Bits: [55:55]

uint32_t roguexe_max_num_cdm_tasks

The maximum number of compute tasks allowed on each USC, range 0 to 48.

Bits: [24:31]

uint32_t roguexe_max_num_pdm_tasks

The maximum number of pixel tasks allowed on each USC, range 0 to 48.

Bits: [16:23]

uint32_t roguexe_max_num_vdm_tasks

The maximum number of vertex tasks (VS, HS, GS when Tess not enabled) allowed on each USC, range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock).

Bits: [8:15]

uint32_t max_num_cdm_tasks

The maximum number of compute tasks allowed on each USC, range 0 to 48.

Bits: [24:30]

uint32_t max_num_pdm_tasks

The maximum number of pixel tasks allowed on each USC, range 0 to 48.

Bits: [16:22]

uint32_t max_num_vdm_tasks

The maximum number of vertex tasks (VS, HS, GS when Tess not enabled) allowed on each USC, range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock).

Bits: [8:14]

ROGUE_CR_EVENT_PIXEL_PDS_CODE_length

Number of 32-bit words used to encode ROGUE_CR_EVENT_PIXEL_PDS_CODE

ROGUE_CR_EVENT_PIXEL_PDS_DATA_length

Number of 32-bit words used to encode ROGUE_CR_EVENT_PIXEL_PDS_DATA

ROGUE_CR_EVENT_PIXEL_PDS_INFO_length

Number of 32-bit words used to encode ROGUE_CR_EVENT_PIXEL_PDS_INFO

ROGUE_CR_PDS_BGRND0_BASE_length

Number of 32-bit words used to encode ROGUE_CR_PDS_BGRND0_BASE

ROGUE_CR_PDS_BGRND1_BASE_length

Number of 32-bit words used to encode ROGUE_CR_PDS_BGRND1_BASE

ROGUE_CR_PDS_BGRND2_BASE_length

Number of 32-bit words used to encode ROGUE_CR_PDS_BGRND2_BASE

ROGUE_CR_PDS_BGRND3_SIZEINFO_length

Number of 32-bit words used to encode ROGUE_CR_PDS_BGRND3_SIZEINFO

struct ROGUE_CR_PDS_BGRND3_SIZEINFO

If any of the size fields are 0, then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128-bit words.

uint32_t usc_sharedsize

The common store allocation size for the shared registers (texture and uniform data combined).

Bits: [55:63]

uint32_t pds_batchnum

The batch ID to be associated with the background.

Bits: [32:45]

uint32_t pds_uniformsize

The size of the Uniform PDS Data Segment in 128-bit words.

Bits: [23:31]

uint32_t pds_texturestatesize

The size of the Texture PDS Data Segment in 128-bit words.

Bits: [16:22]

uint32_t pds_varyingsize

The size of the Varying/Coefficient PDS Data Segment in 128-bit words.

Bits: [10:15]

uint32_t usc_varyingsize

The size of the Varying/Coefficient USC Common Store Data in 4x128-bit words.

Bits: [4:9]

uint32_t pds_tempsize

0 = 0 128-bit words, 1 = 1 128-bit word, this applies to coefficient, uniform and varying state.

Bits: [0:3]

ROGUE_CR_TE_AA_length

Number of 32-bit words used to encode ROGUE_CR_TE_AA

struct ROGUE_CR_TE_AA

This register controls the anti-aliasing mode of the Tiling Co-Processor, independent control is provided in both the X and Y axis. This register needs to be set based on the ISP Samples Per Pixel a core supports.

When ISP Samples Per Pixel = 1: 2xMSAA is achieved by enabling Y - TE does AA on Y plane only 4xMSAA is achieved by enabling Y and X - TE does AA on X and Y plane 8xMSAA not supported by XE cores

When ISP Samples Per Pixel = 2: 2xMSAA is achieved by enabling X2 - does not affect TE 4xMSAA is achieved by enabling Y and X2 - TE does AA on Y plane only 8xMSAA is achieved by enabling Y, X and X2 - TE does AA on X and Y plane 8xMSAA not supported by XE cores

When ISP Samples Per Pixel = 4: 2xMSAA is achieved by enabling X2 - does not affect TE 4xMSAA is achieved by enabling Y2 and X2 - TE does AA on Y plane only 8xMSAA not supported by XE cores

bool y2

Indicates 4xMSAA when X2 and Y2 are set to 1. This does not affect TE and is only used within TPW.

Bits: [3:3]

bool y

Anti-Aliasing in Y Plane Enabled.

Bits: [2:2]

bool x

Anti-Aliasing in X Plane Enabled.

Bits: [1:1]

bool x2

2x Anti-Aliasing Enabled, affects PPP only.

Bits: [0:0]

ROGUE_CR_TE_MTILE1_length

Number of 32-bit words used to encode ROGUE_CR_TE_MTILE1

struct ROGUE_CR_TE_MTILE1

MacroTile Boundaries X Plane.

uint32_t x1

X1 MacroTile boundary, left tile X for second column of macrotiles (16MT mode) - 32 pixels across tile.

Bits: [18:26]

uint32_t x2

X2 MacroTile boundary, left tile X for third column of macrotiles (16MT mode) - 32 pixels across tile.

Bits: [9:17]

uint32_t x3

X3 MacroTile boundary, left tile X for fourth column of macrotiles (16MT mode) - 32 pixels across tile.

Bits: [0:8]

ROGUE_CR_TE_MTILE2_length

Number of 32-bit words used to encode ROGUE_CR_TE_MTILE2

struct ROGUE_CR_TE_MTILE2

MacroTile Boundaries Y Plane.

uint32_t y1

X1 MacroTile boundary, top tile Y for second column of macrotiles (16MT mode) - 32 pixels tile height.

Bits: [18:26]

uint32_t y2

X2 MacroTile boundary, top tile Y for third column of macrotiles (16MT mode) - 32 pixels tile height.

Bits: [9:17]

uint32_t y3

X3 MacroTile boundary, top tile Y for fourth column of macrotiles (16MT mode) - 32 pixels tile height.

Bits: [0:8]

ROGUE_CR_TE_SCREEN_length

Number of 32-bit words used to encode ROGUE_CR_TE_SCREEN

struct ROGUE_CR_TE_SCREEN

In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis.

uint32_t ymax

Maximum Y tile address visible on screen, 32 pixel tile height, 16Kx16K max screen size.

Bits: [12:20]

uint32_t xmax

Maximum X tile address visible on screen, 32 pixel tile width, 16Kx16K max screen size.

Bits: [0:8]

ROGUE_CR_TE_PSG_length

Number of 32-bit words used to encode ROGUE_CR_TE_PSG

struct ROGUE_CR_TE_PSG

This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor.

uint32_t force_protect

When set, the TE will force the PROTECT bit to 1 for all tiles.

Bits: [22:22]

uint32_t cs_size
  • Size of control stream chunk.

    0x0 512-bit. 0x1 1024-bit.

  • Bits: [21:21]

bool enable_pwr_gate_state

Enables TE PSG power gate state init.

Bits: [20:20]

bool enable_context_state_restore

Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set, when reset current local value is preserved.

Bits: [19:19]

bool zonlyrender
  • Don’t invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0

    0x0 Do Invalidate. 0x1 Don’t Invalidate.

  • Bits: [18:18]

bool completeonterminate
  • 0x1 Write region headers, terminate streams and invalidate tail pointer cache entries on terminate.

    0x0 If ZONLYRENDER = 0x0 then force an Interrupt, however if ZONLYRENDER = 0x1 then write region headers and terminate streams.

  • Bits: [17:17]

bool cache_bypass

When set, PSG sets its write only cache to bypass mode, effectively disabling the cache.

Bits: [14:14]

bool forcenewstate

Always embed state information in control stream. Debug only.

Bits: [13:13]

uint32_t region_stride

Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500.

Bits: [0:10]

ROGUE_CR_TE_PSGREGION_ADDR_length

Number of 32-bit words used to encode ROGUE_CR_TE_PSGREGION_ADDR

struct ROGUE_CR_TE_PSGREGION_ADDR

This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to parameters.

uint64_t base

16GB Addressable, 512-bit aligned Base Address for Region Header writes.

Bits: [6:33]

ROGUE_CR_TE_TPC_ADDR_length

Number of 32-bit words used to encode ROGUE_CR_TE_TPC_ADDR

struct ROGUE_CR_TE_TPC_ADDR

This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tile’s individual display list, an entry for active tiles is maintained as primitives are processed by the TA.

uint64_t base

16GB Addressable, 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile.

Bits: [6:33]

ROGUE_CR_PPP_MULTISAMPLECTL_length

Number of 32-bit words used to encode ROGUE_CR_PPP_MULTISAMPLECTL

struct ROGUE_CR_PPP_MULTISAMPLECTL

Sample position grid offset for use in 2x, 4x, 8xMSAA and ODAA modes.

uint32_t msaa_y7

Unsigned sub-pixel offset for the 8th multisample Y position.

Bits: [60:63]

uint32_t msaa_x7

Unsigned sub-pixel offset for the 8th multisample X position.

Bits: [56:59]

uint32_t msaa_y6

Unsigned sub-pixel offset for the 7th multisample Y position.

Bits: [52:55]

uint32_t msaa_x6

Unsigned sub-pixel offset for the 7th multisample X position.

Bits: [48:51]

uint32_t msaa_y5

Unsigned sub-pixel offset for the 6th multisample Y position.

Bits: [44:47]

uint32_t msaa_x5

Unsigned sub-pixel offset for the 6th multisample X position.

Bits: [40:43]

uint32_t msaa_y4

Unsigned sub-pixel offset for the 5th multisample Y position.

Bits: [36:39]

uint32_t msaa_x4

Unsigned sub-pixel offset for the 5th multisample X position.

Bits: [32:35]

uint32_t msaa_y3

Unsigned sub-pixel offset for the 4th multisample Y position.

Bits: [28:31]

uint32_t msaa_x3

Unsigned sub-pixel offset for the 4th multisample X position.

Bits: [24:27]

uint32_t msaa_y2

Unsigned sub-pixel offset for the 3rd multisample Y position.

Bits: [20:23]

uint32_t msaa_x2

Unsigned sub-pixel offset for the 3rd multisample X position.

Bits: [16:19]

uint32_t msaa_y1

Unsigned sub-pixel offset for the 2nd multisample Y position.

Bits: [12:15]

uint32_t msaa_x1

Unsigned sub-pixel offset for the 2nd multisample X position.

Bits: [8:11]

uint32_t msaa_y0

Unsigned sub-pixel offset for the 1st multisample Y position.

Bits: [4:7]

uint32_t msaa_x0

Unsigned sub-pixel offset for the 1st multisample X position.

Bits: [0:3]

ROGUE_CR_PPP_CTRL_length

Number of 32-bit words used to encode ROGUE_CR_PPP_CTRL

struct ROGUE_CR_PPP_CTRL

This register controls the global setup of the PPP.

bool vpt_scissor
  • When 0 the PPP will insert state updates on change of VPT ID.

    When 1 this feature is disabled.

  • Bits: [12:12]

uint32_t flush_mode
  • When 0 PPP will suppress end of draw call flushed from reaching the Clipper and TA pipeline. This will break batch number functionality but will give better primitive block utilisation.

    When 1 PPP will not suppress any flushes.

  • Bits: [11:11]

bool bfcull_restrict_clip
  • When set, clipped primitives are only back-face culled after the clipper.

    0 Enable early back face cull for clipped primitives. 1 Disable early cull.

  • Bits: [10:10]

uint32_t fixed_point_format
  • When set, the PPP will use a fixed point format of 16.8 rather than 16.4.

    0 16.4 fixed point format. 1 16.8 fixed point format.

  • Bits: [9:9]

bool default_point_size
  • When set, the PPP will use the default point size rather than reading it from the vertex.

    0 Point size read from vertex. 1 Default point size of 3F800000 used.

  • Bits: [8:8]

bool bfcull1_disable
  • Disable for fully clipped culling.

    0 First back face cull block enabled. 1 First back face cull block disabled.

  • Bits: [7:7]

bool bfcull2_disable
  • Disable for fully clipped culling.

    0 Second back face cull block enabled. 1 Second back face cull block disabled.

  • Bits: [6:6]

bool fccull_disable
  • Disable for fully clipped culling.

    0 Fully clipped culling enabled. 1 Fully clipped culling disabled.

  • Bits: [5:5]

bool oscull_disable
  • Disable for off screen culling.

    0 Off screen culling enabled. 1 Off screen culling disabled.

  • Bits: [4:4]

bool socull_disable
  • Disable for small object culling.

    0 Small object culling enabled. 1 Small object culling disabled.

  • Bits: [2:2]

bool wclampen
  • Enable W clamping.

    0 W clamping disabled. 1 W clamping enabled.

  • Bits: [1:1]

bool opengl
  • Select OpenGL or D3D mode.

    0 D3D. 1 OpenGL.

  • Bits: [0:0]

ROGUE_CR_PPP_SCREEN_length

Number of 32-bit words used to encode ROGUE_CR_PPP_SCREEN

struct ROGUE_CR_PPP_SCREEN

In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X and Y axis since this may not be the same as the number of tiles defined in the ROGUE_CR_TE_SCREEN register.

uint32_t pixymax

Screen height in pixels (16K x 16K max screen size).

Bits: [16:30]

uint32_t pixxmax

Screen width in pixels (16K x 16K max screen size).

Bits: [0:14]

ROGUE_CR_TA_RTC_ADDR_length

Number of 32-bit words used to encode ROGUE_CR_TA_RTC_ADDR

struct ROGUE_CR_TA_RTC_ADDR

This register defines the base address in memory of the TA Render Target Caches, for the VCE, TEAC and PSG.

uint64_t base

16GB Addressable, 512-bit aligned Base Address for TA Render Target Caches.

Bits: [6:33]

ROGUE_CR_TA_CONTEXT_STATE_BASE_length

Number of 32-bit words used to encode ROGUE_CR_TA_CONTEXT_STATE_BASE

struct ROGUE_CR_TA_CONTEXT_STATE_BASE

The base address in external memory of the TA’s context state buffer, to which the PPP will store the state on a context store and from which the VDM will reload on a context resume.

uint64_t addr

1TB range, 128-bit aligned base address.

Bits: [4:39]

ROGUE_CR_ISP_RENDER_length

Number of 32-bit words used to encode ROGUE_CR_ISP_RENDER

struct ROGUE_CR_ISP_RENDER

Controls the render.

bool disable_eomt

Prevent End-of-Macro-Tile flags being sent to ISP.

Bits: [5:5]

bool resume

Render resume.

Bits: [4:4]

enum ROGUE_CR_DIR_TYPE dir_type

Render direction.

Bits: [2:3]

enum ROGUE_CR_ISP_RENDER_MODE_TYPE mode_type

Render type.

Bits: [0:1]

ROGUE_CR_ISP_RENDER_ORIGIN_length

Number of 32-bit words used to encode ROGUE_CR_ISP_RENDER_ORIGIN

struct ROGUE_CR_ISP_RENDER_ORIGIN

This register defines the top-left tile coordinate for the render.

uint32_t x

X coordinate, in tiles.

Bits: [16:25]

uint32_t y

Y coordinate, in tiles.

Bits: [0:9]

ROGUE_CR_ISP_MTILE_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_MTILE_BASE

ROGUE_CR_ISP_MTILE_SIZE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_MTILE_SIZE

ROGUE_CR_ISP_RGN_length

Number of 32-bit words used to encode ROGUE_CR_ISP_RGN

struct ROGUE_CR_ISP_RGN

This register defines the size of the allocation used for Region Arrays. This is used to read the correct number of words from memory without the risk of over-fetching and causing a page fault.

uint32_t size

Number of DWords to fetch from each Region Array.

Bits: [0:23]

ROGUE_CR_ISP_RGN_SIPF_length

Number of 32-bit words used to encode ROGUE_CR_ISP_RGN_SIPF

struct ROGUE_CR_ISP_RGN_SIPF

This register defines the sizes of the allocations of the simple internal parameter data.

uint32_t cs_size_ipf_creq_pf

Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown, a value of all ones should be written.

Bits: [24:28]

uint32_t size

Number of Region Headers to fetch.

Bits: [0:23]

ROGUE_CR_ISP_BGOBJDEPTH_length

Number of 32-bit words used to encode ROGUE_CR_ISP_BGOBJDEPTH

struct ROGUE_CR_ISP_BGOBJDEPTH

The ISP operates by comparing depth values of incoming objects with the results of previous depth compares, in order to make sure there are no uninitialised values at the start of the tile or to cover pixels where there are no objects in the scene, a default background object is configured under register control. This register provides the floating point depth value for the hardware background object.

uint32_t value
  • Note, the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register.

    If depth buffer is F32, then the value here should be IEEE 754 single precision floating point. If depth buffer is INT16,then the value here should be UNORM24/UNORM16 format as well. Out of Range value will cause undefined behaviour.

  • Bits: [0:31]

ROGUE_CR_ISP_BGOBJVALS_length

Number of 32-bit words used to encode ROGUE_CR_ISP_BGOBJVALS

struct ROGUE_CR_ISP_BGOBJVALS

This register provides enable, mask and stencil information for the hardware background object.

bool enablebgtag

When set to 1, at the start of each tile the ISP tag buffer is initialised with the background object tag (default = 1).

Bits: [9:9]

bool mask

Hardware background object mask plane.

Bits: [8:8]

uint32_t stencil

Hardware background object stencil.

Bits: [0:7]

ROGUE_CR_ISP_AA_length

Number of 32-bit words used to encode ROGUE_CR_ISP_AA

struct ROGUE_CR_ISP_AA

Controls whether anti-aliasing is enabled or disabled.

enum ROGUE_CR_ISP_AA_MODE_TYPE mode

Bits: [0:1] Default: AA_NONE

ROGUE_CR_ISP_CTL_length

Number of 32-bit words used to encode ROGUE_CR_ISP_CTL

struct ROGUE_CR_ISP_CTL

ISP control register.

This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight that are desired, but also the version of the architecture in use.

For REL 1,2 Cores, this register can be programmed to values of 0x0-0x2 inclusive enabling 1,2 and 3 tiles in flight for the single ISP in the system. In this system the IPP and IPF are both present in the same layout block.

For REL 3,7 Cores, the IPP module is remote from the ISP module as the ISP belongs to the scalable elements in the design. A Cluster Group refers to the 4 USCs in a Phantom Block, which also contains an ISP. 1 Cluster Group = 1 IPP, and 1 ISP, 2 Cluster Groups = 1 IPP and 2 ISPs. The IPP module is configured using the register, and the tiles are split between them via the LSB of the Pipe Identifier.

When 2 Cluster Groups (6 or 8 USC clusters) are present, as the value of PIPE_NUM is increased, the tile in flight are spread equally between ISP0 and ISP1, as below 0x0: - ISP0 (1 tile in flight) - ISP1 (Not Used - IDLE Pipe) 0x1: - ISP0 (1 tile in flight) - ISP1 (1 tile in flight) 0x2: - ISP0 (2 tiles in flight) - ISP1 (1 tile in flight) 0x3: - ISP0 (2 tiles in flight) - ISP1 (2 tiles in flight) 0x4: - ISP0 (3 tiles in flight) - ISP1 (2 tiles in flight) 0x5: - ISP0 (3 tiles in flight) - ISP1 (3 tiles in flight) 0x6: - ISP0 (4 tiles in flight) - ISP1 (3 tiles in flight) 0x7: - ISP0 (4 tiles in flight) - ISP1 (4 tiles in flight)

Value of 0,2,4,6 should never be use on a 8 USC system, as they result in internal GPU imbalance.

When 1 Cluster Group is present (1,2,4 USC clusters) , as the value of PIPE_NUM is increased, the tiles in flight will increase every power of 2, since ISP1 is not present. 0x0: - ISP0 (1 tile in flight) 0x2: - ISP0 (2 tiles in flight) 0x4: - ISP0 (3 tiles in flight) 0x6: - ISP0 (4 tiles in flight)

A value which is higher than the number of IPF pipelines will result in the maximum number of pipelines being used. However, the number of pipelines being used should always be less than or equal to the number of tiles which the USC is able to concurrently process (i.e. the number of partitions). In a 4 or 8 cluster system there is 1 partition per tile. In a 2 cluster system there are 2 partitions per tile and in a 1 cluster system there are 4 partitions per tile. Effectively this means this register should be programmed according to the number of partitions available in the USC.

NUM_TILES_PER_USC: 00 : 1 tile. 01 : 2 tiles in the flight per USC cluster enabled. 11 : 2 tiles in the flight per USC cluster enabled.

bool skip_init_hdrs
  • Used to enable skipping of initial region headers based on GPU offset.

    ‘0’: reads all region headers and discards the ones not needed. ‘1’: skip reading of region headers based on GPU offset.

  • Bits: [31:31]

bool line_style
  • Used to enable rendering widelines as rectangles.

    ‘0’: render as parallelograms. ‘1’: render as rectangles.

  • Bits: [30:30]

bool line_style_pix
  • Used to enable rendering single pixel widelines as rectangles.

    ‘0’: render as parallelograms. ‘1’: render as rectangles.

  • Bits: [29:29]

bool pair_tiles_vert

If set, causes IPF to pair tiles vertically within its pipeline.

Bits: [28:28]

bool pair_tiles

If set, causes IPF to pair tiles within its pipeline.

Bits: [27:27]

uint32_t num_tiles_per_usc

Tiles-in-flight per USC cluster.

Bits: [21:22]

bool dbias_is_int

When set, depth bias value is a signed integer.

Bits: [20:20]

bool overlap_check_mode
  • 0 - different samples for the same pixel will be sent to different pass groups for translucent objects (pixel to pixel overlap test).

    1 - different samples for the same pixel will be sent as the same pass group (sample to sample overlap test).

  • Bits: [19:19]

bool pt_upfront_depth_disable

When set, disable UPFRONT depth test in the Depthsorter.

Bits: [18:18]

bool process_empty_tiles

When set empty tiles are always processed rather than being suppressed.

Bits: [17:17]

bool sample_pos

Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines.

Bits: [16:16]

enum ROGUE_CR_PIPE_NUM pipe_enable

Tiles-in-flight.

Bits: [12:15]

uint32_t valid_id

Triangle validation value.

Bits: [4:9]

uint32_t upass_start

User pass start value.

Bits: [0:3]

ROGUE_CR_ISP_ZLSCTL_length

Number of 32-bit words used to encode ROGUE_CR_ISP_ZLSCTL

ROGUE_CR_ISP_ZLOAD_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_ZLOAD_BASE

struct ROGUE_CR_ISP_ZLOAD_BASE

Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats.

uint64_t addr

1TB Addressable, 16byte aligned Base Address of the Z Buffer Load base address.

Bits: [4:39]

ROGUE_CR_ISP_STENCIL_LOAD_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_STENCIL_LOAD_BASE

struct ROGUE_CR_ISP_STENCIL_LOAD_BASE

Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit.

uint64_t addr

1TB Addressable, 16byte aligned Base Address of the Z Buffer Load base address.

Bits: [4:39]

bool enable

When set to 1, enables fetching of stencil from a separate base address.

Bits: [0:0]

ROGUE_CR_ISP_SCISSOR_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_SCISSOR_BASE

ROGUE_CR_ISP_DBIAS_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_DBIAS_BASE

ROGUE_CR_ISP_OCLQRY_BASE_length

Number of 32-bit words used to encode ROGUE_CR_ISP_OCLQRY_BASE

struct ROGUE_CR_ISP_OCLQRY_BASE

Base address for occlusion query counter values. For multiple phantom system, base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index.

uint64_t addr

1TB range, 128-bit aligned base address.

Bits: [4:39]

ROGUE_CR_ISP_ZLS_PIXELS_length

Number of 32-bit words used to encode ROGUE_CR_ISP_ZLS_PIXELS

struct ROGUE_CR_ISP_ZLS_PIXELS

Screen size in pixel numbers for ZLS.

uint32_t y
  • Display width of Y in pixels minus one.

    0x000 1 pixel, 0x001 2 pixels, …, 0x7FFF 1024*32 pixels. Subtile only supports for non-MSAA mode depth load/store, so For non-MSAA mode, if framebuffer compression, or separate mask or separate stencil is enabled, [4 .. 0] has to be set to x”1F”. For 2xMSAA mode, [4 .. 0] has to be set to x”1F”. For 4xMSAA mode, [3 .. 0] has to be set to x”F”. For 8xMSAA mode, [3 .. 0] has to be set to x”F”.

  • Bits: [15:29]

uint32_t x
  • Display width of X in pixels minus one.

    0x000 1 pixel, 0x001 2 pixels, …, 0x7FFF 1024*32 pixels. Subtile only supports for non-MSAA mode depth load/store, so For non-MSAA mode, if framebuffer compression, or separate mask or separate stencil is enabled, [4 .. 0] has to be set to x”1F”. For 2xMSAA mode, [4 .. 0] has to be set to x”1F”. For 4xMSAA mode, [4 .. 0] has to be set to x”1F”. For 8xMSAA mode, [3 .. 0] has to be set to x”F”.

  • Bits: [0:14]

ROGUE_CR_PBE_WORD0_MRT0_length

Number of 32-bit words used to encode ROGUE_CR_PBE_WORD0_MRT0

ROGUE_CR_FRAG_SCREEN_length

Number of 32-bit words used to encode ROGUE_CR_FRAG_SCREEN

struct ROGUE_CR_FRAG_SCREEN

Define the screen size for fragment processing. Pixels on the screen are numbered (0,0) top left, to (XMAX,YMAX) bottom right.

uint32_t ymax
  • Maximum pixel number in y dimension on screen. Screen height in pixels is YMAX+1.

    16K x 16K is the max screen size. I.e. 2^14, bit 15 is always written as 0.

  • Bits: [16:30]

uint32_t xmax
  • Maximum pixel number in x dimension on screen. Screen width in pixels is XMAX+1.

    16K x 16K is the max screen size. I.e. 2^14, bit 15 is always written as 0.

  • Bits: [0:14]

ROGUE_CR_TPU_length

Number of 32-bit words used to encode ROGUE_CR_TPU

ROGUE_CR_TPU_BORDER_COLOUR_TABLE_PDM_length

Number of 32-bit words used to encode ROGUE_CR_TPU_BORDER_COLOUR_TABLE_PDM

struct ROGUE_CR_TPU_BORDER_COLOUR_TABLE_PDM

Base address for the border colour table.

uint64_t border_colour_table_address

Base address DWord aligned for the location in memory of the border colour table for the PDM.

Bits: [0:37]

ROGUE_CR_TPU_BORDER_COLOUR_TABLE_VDM_length

Number of 32-bit words used to encode ROGUE_CR_TPU_BORDER_COLOUR_TABLE_VDM

struct ROGUE_CR_TPU_BORDER_COLOUR_TABLE_VDM

Base address for the border colour table.

uint64_t border_colour_table_address

Base address DWord aligned for the location in memory of the border colour table for the VDM.

Bits: [0:37]

ROGUE_CR_TPU_BORDER_COLOUR_TABLE_CDM_length

Number of 32-bit words used to encode ROGUE_CR_TPU_BORDER_COLOUR_TABLE_CDM

struct ROGUE_CR_TPU_BORDER_COLOUR_TABLE_CDM

Base address for the border colour table.

uint64_t border_colour_table_address

Base address DWord aligned for the location in memory of the border colour table for the CDM.

Bits: [0:37]

ROGUE_CR_TPU_TAG_CDM_CTRL_length

Number of 32-bit words used to encode ROGUE_CR_TPU_TAG_CDM_CTRL

ROGUE_CR_USC_PIXEL_OUTPUT_CTRL_length

Number of 32-bit words used to encode ROGUE_CR_USC_PIXEL_OUTPUT_CTRL

ROGUE_CR_USC_CLEAR_REGISTER_length

Number of 32-bit words used to encode ROGUE_CR_USC_CLEAR_REGISTER

ROGUE_CR_FB_CDC_ZLS_length

Number of 32-bit words used to encode ROGUE_CR_FB_CDC_ZLS

IPF (Internal Parameter Format)

API documentation for Internal Parameter Format structures and functions:

enum ROGUE_IPF_COMPRESSION_FORMAT

Encoding of COMPRESSION_FORMAT fields.

enum ROGUE_IPF_CS_MASK_FMT

Encoding of CS_MASK_FMT field.

enum ROGUE_IPF_CS_TYPE

Encoding of CS_TYPE field.

enum ROGUE_IPF_CS_CTRL_TYPE_SIPF2

Encoding of CS_CTRL_TYPE field.

ROGUE_IPF_INDEX_DATA_WORDS_SIPF_length

Number of 32-bit words used to encode ROGUE_IPF_INDEX_DATA_WORDS_SIPF

struct ROGUE_IPF_INDEX_DATA_WORDS_SIPF

Labelling of fields within Index Data.

bool ix_triangle3_bf_flag

Bits: [63:63]

bool ix_triangle3_edge_flag_ca

Bits: [62:62]

uint32_t ix_triangle3_index_2

Bits: [58:61]

bool ix_triangle3_edge_flag_bc

Bits: [57:57]

uint32_t ix_triangle3_index_1

Bits: [53:56]

bool ix_triangle3_edge_flag_ab

Bits: [52:52]

uint32_t ix_triangle3_index_0

Bits: [48:51]

bool ix_triangle2_bf_flag

Bits: [47:47]

bool ix_triangle2_edge_flag_ca

Bits: [46:46]

uint32_t ix_triangle2_index_2

Bits: [42:45]

bool ix_triangle2_edge_flag_bc

Bits: [41:41]

uint32_t ix_triangle2_index_1

Bits: [37:40]

bool ix_triangle2_edge_flag_ab

Bits: [36:36]

uint32_t ix_triangle2_index_0

Bits: [32:35]

bool ix_triangle1_bf_flag

Bits: [31:31]

bool ix_triangle1_edge_flag_ca

Bits: [30:30]

uint32_t ix_triangle1_index_2

Bits: [26:29]

bool ix_triangle1_edge_flag_bc

Bits: [25:25]

uint32_t ix_triangle1_index_1

Bits: [21:24]

bool ix_triangle1_edge_flag_ab

Bits: [20:20]

uint32_t ix_triangle1_index_0

Bits: [16:19]

bool ix_triangle0_bf_flag

Bits: [15:15]

bool ix_triangle0_edge_flag_ca

Bits: [14:14]

uint32_t ix_triangle0_index_2

Bits: [10:13]

bool ix_triangle0_edge_flag_bc

Bits: [9:9]

uint32_t ix_triangle0_index_1

Bits: [5:8]

bool ix_triangle0_edge_flag_ab

Bits: [4:4]

uint32_t ix_triangle0_index_0

Bits: [0:3]

ROGUE_IPF_VERTEX_FORMAT_WORD_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_VERTEX_FORMAT_WORD_SIPF2

struct ROGUE_IPF_VERTEX_FORMAT_WORD_SIPF2

This contains information such as number of vertices in the primitive block and more information about the structure of the primitive block. It is stored in the memory at CS_PRIM_BASE, along with optional ISP State Words.

uint32_t vf_isp_format_word

Offset in 64-bit words from the 1st ISP vertex word to the 1st PDS state word.

Bits: [42:63]

uint32_t vf_isp_state_size

ISP state size in units of 32-bit words.

Bits: [39:41]

bool vf_tsp_vtx_raw

If set, TSP varyings are not compressed and there are no TSP varying floor or format fields present.

Bits: [38:38]

bool vf_isp_vtx_raw

If set, ISP vertices are not compressed and there are no ISP vertex floor or format fields present.

Bits: [37:37]

uint32_t vf_varying_total_16

Total number of 16-bit varyings per vertex.

Bits: [30:36]

uint32_t vf_varying_total_32

Total number of 32-bit varyings per vertex.

Bits: [23:29]

uint32_t vf_varying_vertex_bits

Compressed varying size per vertex in bits.

Bits: [11:22]

uint32_t vf_primitive_total

The number of primitives in the primitive block minus 1 i.e. 0 means 1 primitive.

Bits: [6:10]

uint32_t vf_vertex_total

The number of vertices in the primitive block minus 1 i.e. 0 means 1 vertex.

Bits: [2:5]

bool vf_prim_msaa_disable

If set, MSAA is disabled in this primitive block and all pixel sub-samples are rasterised at the default grid offset.

Bits: [1:1]

bool vf_vertex_clipped

If set, TSP Vertex data has been generated by the clipper.

Bits: [0:0]

ROGUE_IPF_SCISSOR_WORD_0_length

Number of 32-bit words used to encode ROGUE_IPF_SCISSOR_WORD_0

struct ROGUE_IPF_SCISSOR_WORD_0

Labelling of fields within Scissor Word 0.

uint32_t scw0_xmin

Xmin (unsigned int).

Bits: [16:31]

uint32_t scw0_xmax

Xmax (unsigned int).

Bits: [0:15]

ROGUE_IPF_SCISSOR_WORD_1_length

Number of 32-bit words used to encode ROGUE_IPF_SCISSOR_WORD_1

struct ROGUE_IPF_SCISSOR_WORD_1

Labelling of fields within Scissor Word 1.

uint32_t scw1_ymin

Ymin (unsigned int).

Bits: [16:31]

uint32_t scw1_ymax

Ymax (unsigned int).

Bits: [0:15]

ROGUE_IPF_CONTROL_STREAM_length

Number of 32-bit words used to encode ROGUE_IPF_CONTROL_STREAM

struct ROGUE_IPF_CONTROL_STREAM

Labelling of fields within Control Stream.

enum ROGUE_IPF_CS_TYPE cs_type

Control stream ID.

Bits: [30:31]

A 1024-bit aligned address which is capable of accessing a 16 GB range.

Bits: [3:29]

Number of 32-bit words used to encode ROGUE_IPF_CONTROL_STREAM_LINK_SIPF2

Labelling of fields within Control Stream.

A 512-bit aligned address which is capable of accessing a 16 GB range.

Bits: [2:31]

01b Stream Link.

Bits: [0:1] Default: LINK

ROGUE_IPF_CONTROL_STREAM_TERMINATE_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_CONTROL_STREAM_TERMINATE_SIPF2

struct ROGUE_IPF_CONTROL_STREAM_TERMINATE_SIPF2

Labelling of fields within Control Stream.

uint32_t rsvd

Reserved.

Bits: [2:7]

enum ROGUE_IPF_CS_CTRL_TYPE_SIPF2 cs_ctrl_type

11b Stream Terminate.

Bits: [0:1] Default: TERM

ROGUE_IPF_PRIMITIVE_HEADER_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_PRIMITIVE_HEADER_SIPF2

struct ROGUE_IPF_PRIMITIVE_HEADER_SIPF2

Labelling of fields within Primitive Format.

bool cs_valid_tile3

If set, then there is at least 1 primitive in this primitive block in tile 3.

Bits: [7:7]

bool cs_valid_tile2

If set, then there is at least 1 primitive in this primitive block in tile 2.

Bits: [6:6]

bool cs_valid_tile1

If set, then there is at least 1 primitive in this primitive block in tile 1.

Bits: [5:5]

bool cs_valid_tile0

If set, then there is at least 1 primitive in this primitive block in tile 0.

Bits: [4:4]

uint32_t cs_mask_num_bytes

The size of each tile bit-based mask in bytes, between 1 to 3 bytes. 1 = 1 byte, 2 = 2 bytes, 3 = 3 bytes, 0 = reserved.

Bits: [2:3]

bool cs_prim_base_size

If set, then the (full) Primitive Base word is present for the primitive block. If not set, the Primitive Base Offset is present for the primitive block.

Bits: [1:1]

enum ROGUE_IPF_CS_CTRL_TYPE_SIPF2 cs_ctrl_type

00b Primitive Block.

Bits: [0:0] Default: PRIM

ROGUE_IPF_PRIMITIVE_FORMAT_length

Number of 32-bit words used to encode ROGUE_IPF_PRIMITIVE_FORMAT

struct ROGUE_IPF_PRIMITIVE_FORMAT

Labelling of fields within Primitive Format.

enum ROGUE_IPF_CS_TYPE cs_type

00b Primitive Block.

Bits: [30:31]

bool cs_isp_state_read

If set, then ISP state must be read from the primitive block.

Bits: [29:29]

uint32_t cs_isp_state_size

The total number of ISP state words in the primitive block.

Bits: [26:28]

uint32_t cs_prim_total

The number of primitives in the primitive block minus 1 i.e. 0 means 1 primitive.

Bits: [19:25]

enum ROGUE_IPF_CS_MASK_FMT cs_mask_fmt

The format of the encoding of primitive mask data for the primitive block.

Bits: [17:18]

bool cs_prim_base_pres

If set, then the Primitive Base Pointer word is present for the primitive block. Always set when using a byte-based primitive mask.

Bits: [16:16]

uint32_t cs_prim_base_offset

This is a 32-bit aligned, unsigned offset which is capable of accessing a 256 KB range. This offset replaces the 16 LSBs of the previous primitive base in order to generate the current primitive base.

Bits: [0:15]

ROGUE_IPF_PRIMITIVE_BASE_length

Number of 32-bit words used to encode ROGUE_IPF_PRIMITIVE_BASE

struct ROGUE_IPF_PRIMITIVE_BASE

Labelling of fields within Primitive Base.

uint64_t cs_prim_base

A 32-bit aligned address which is capable of accessing a 16 GB range.

Bits: [0:31]

ROGUE_IPF_PRIMITIVE_BASE_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_PRIMITIVE_BASE_SIPF2

struct ROGUE_IPF_PRIMITIVE_BASE_SIPF2

Labelling of fields within Primitive Base.

uint64_t cs_prim_base

A 64-bit aligned address which is capable of accessing a 32 GB range.

Bits: [0:31]

ROGUE_IPF_BYTE_BASED_MASK_ONE_BYTE_WORD_0_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_ONE_BYTE_WORD_0_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_ONE_BYTE_WORD_0_SIPF2

Labelling of fields within Byte Based Mask One-Byte Word 0.

bool cs_mask_one_byte_tile3_7

When set, primitive 7 is present in tile 3.

Bits: [31:31]

bool cs_mask_one_byte_tile3_6

When set, primitive 6 is present in tile 3.

Bits: [30:30]

bool cs_mask_one_byte_tile3_5

When set, primitive 5 is present in tile 3.

Bits: [29:29]

bool cs_mask_one_byte_tile3_4

When set, primitive 4 is present in tile 3.

Bits: [28:28]

bool cs_mask_one_byte_tile3_3

When set, primitive 3 is present in tile 3.

Bits: [27:27]

bool cs_mask_one_byte_tile3_2

When set, primitive 2 is present in tile 3.

Bits: [26:26]

bool cs_mask_one_byte_tile3_1

When set, primitive 1 is present in tile 3.

Bits: [25:25]

bool cs_mask_one_byte_tile3_0

When set, primitive 0 is present in tile 3.

Bits: [24:24]

bool cs_mask_one_byte_tile2_7

When set, primitive 7 is present in tile 2.

Bits: [23:23]

bool cs_mask_one_byte_tile2_6

When set, primitive 6 is present in tile 2.

Bits: [22:22]

bool cs_mask_one_byte_tile2_5

When set, primitive 5 is present in tile 2.

Bits: [21:21]

bool cs_mask_one_byte_tile2_4

When set, primitive 4 is present in tile 2.

Bits: [20:20]

bool cs_mask_one_byte_tile2_3

When set, primitive 3 is present in tile 2.

Bits: [19:19]

bool cs_mask_one_byte_tile2_2

When set, primitive 2 is present in tile 2.

Bits: [18:18]

bool cs_mask_one_byte_tile2_1

When set, primitive 1 is present in tile 2.

Bits: [17:17]

bool cs_mask_one_byte_tile2_0

When set, primitive 0 is present in tile 2.

Bits: [16:16]

bool cs_mask_one_byte_tile1_7

When set, primitive 7 is present in tile 1.

Bits: [15:15]

bool cs_mask_one_byte_tile1_6

When set, primitive 6 is present in tile 1.

Bits: [14:14]

bool cs_mask_one_byte_tile1_5

When set, primitive 5 is present in tile 1.

Bits: [13:13]

bool cs_mask_one_byte_tile1_4

When set, primitive 4 is present in tile 1.

Bits: [12:12]

bool cs_mask_one_byte_tile1_3

When set, primitive 3 is present in tile 1.

Bits: [11:11]

bool cs_mask_one_byte_tile1_2

When set, primitive 2 is present in tile 1.

Bits: [10:10]

bool cs_mask_one_byte_tile1_1

When set, primitive 1 is present in tile 1.

Bits: [9:9]

bool cs_mask_one_byte_tile1_0

When set, primitive 0 is present in tile 1.

Bits: [8:8]

bool cs_mask_one_byte_tile0_7

When set, primitive 7 is present in tile 0.

Bits: [7:7]

bool cs_mask_one_byte_tile0_6

When set, primitive 6 is present in tile 0.

Bits: [6:6]

bool cs_mask_one_byte_tile0_5

When set, primitive 5 is present in tile 0.

Bits: [5:5]

bool cs_mask_one_byte_tile0_4

When set, primitive 4 is present in tile 0.

Bits: [4:4]

bool cs_mask_one_byte_tile0_3

When set, primitive 3 is present in tile 0.

Bits: [3:3]

bool cs_mask_one_byte_tile0_2

When set, primitive 2 is present in tile 0.

Bits: [2:2]

bool cs_mask_one_byte_tile0_1

When set, primitive 1 is present in tile 0.

Bits: [1:1]

bool cs_mask_one_byte_tile0_0

When set, primitive 0 is present in tile 0.

Bits: [0:0]

ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_0_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_0_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_0_SIPF2

Labelling of fields within Byte Based Mask Two-Byte Word 0.

bool cs_mask_two_byte_tile1_15

When set, primitive 15 is present in tile 1.

Bits: [31:31]

bool cs_mask_two_byte_tile1_14

When set, primitive 14 is present in tile 1.

Bits: [30:30]

bool cs_mask_two_byte_tile1_13

When set, primitive 13 is present in tile 1.

Bits: [29:29]

bool cs_mask_two_byte_tile1_12

When set, primitive 12 is present in tile 1.

Bits: [28:28]

bool cs_mask_two_byte_tile1_11

When set, primitive 11 is present in tile 1.

Bits: [27:27]

bool cs_mask_two_byte_tile1_10

When set, primitive 10 is present in tile 1.

Bits: [26:26]

bool cs_mask_two_byte_tile1_9

When set, primitive 9 is present in tile 1.

Bits: [25:25]

bool cs_mask_two_byte_tile1_8

When set, primitive 8 is present in tile 1.

Bits: [24:24]

bool cs_mask_two_byte_tile1_7

When set, primitive 7 is present in tile 1.

Bits: [23:23]

bool cs_mask_two_byte_tile1_6

When set, primitive 6 is present in tile 1.

Bits: [22:22]

bool cs_mask_two_byte_tile1_5

When set, primitive 5 is present in tile 1.

Bits: [21:21]

bool cs_mask_two_byte_tile1_4

When set, primitive 4 is present in tile 1.

Bits: [20:20]

bool cs_mask_two_byte_tile1_3

When set, primitive 3 is present in tile 1.

Bits: [19:19]

bool cs_mask_two_byte_tile1_2

When set, primitive 2 is present in tile 1.

Bits: [18:18]

bool cs_mask_two_byte_tile1_1

When set, primitive 1 is present in tile 1.

Bits: [17:17]

bool cs_mask_two_byte_tile1_0

When set, primitive 0 is present in tile 0.

Bits: [16:16]

bool cs_mask_two_byte_tile0_15

When set, primitive 15 is present in tile 0.

Bits: [15:15]

bool cs_mask_two_byte_tile0_14

When set, primitive 14 is present in tile 0.

Bits: [14:14]

bool cs_mask_two_byte_tile0_13

When set, primitive 13 is present in tile 0.

Bits: [13:13]

bool cs_mask_two_byte_tile0_12

When set, primitive 12 is present in tile 0.

Bits: [12:12]

bool cs_mask_two_byte_tile0_11

When set, primitive 11 is present in tile 0.

Bits: [11:11]

bool cs_mask_two_byte_tile0_10

When set, primitive 10 is present in tile 0.

Bits: [10:10]

bool cs_mask_two_byte_tile0_9

When set, primitive 9 is present in tile 0.

Bits: [9:9]

bool cs_mask_two_byte_tile0_8

When set, primitive 8 is present in tile 0.

Bits: [8:8]

bool cs_mask_two_byte_tile0_7

When set, primitive 7 is present in tile 0.

Bits: [7:7]

bool cs_mask_two_byte_tile0_6

When set, primitive 6 is present in tile 0.

Bits: [6:6]

bool cs_mask_two_byte_tile0_5

When set, primitive 5 is present in tile 0.

Bits: [5:5]

bool cs_mask_two_byte_tile0_4

When set, primitive 4 is present in tile 0.

Bits: [4:4]

bool cs_mask_two_byte_tile0_3

When set, primitive 3 is present in tile 0.

Bits: [3:3]

bool cs_mask_two_byte_tile0_2

When set, primitive 2 is present in tile 0.

Bits: [2:2]

bool cs_mask_two_byte_tile0_1

When set, primitive 1 is present in tile 0.

Bits: [1:1]

bool cs_mask_two_byte_tile0_0

When set, primitive 0 is present in tile 0.

Bits: [0:0]

ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_1_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_1_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_TWO_BYTE_WORD_1_SIPF2

Labelling of fields within Byte Based Mask Two-Byte Word 1.

bool cs_mask_two_byte_tile3_15

When set, primitive 15 is present in tile 3.

Bits: [31:31]

bool cs_mask_two_byte_tile3_14

When set, primitive 14 is present in tile 3.

Bits: [30:30]

bool cs_mask_two_byte_tile3_13

When set, primitive 13 is present in tile 3.

Bits: [29:29]

bool cs_mask_two_byte_tile3_12

When set, primitive 12 is present in tile 3.

Bits: [28:28]

bool cs_mask_two_byte_tile3_11

When set, primitive 11 is present in tile 3.

Bits: [27:27]

bool cs_mask_two_byte_tile3_10

When set, primitive 10 is present in tile 3.

Bits: [26:26]

bool cs_mask_two_byte_tile3_9

When set, primitive 9 is present in tile 3.

Bits: [25:25]

bool cs_mask_two_byte_tile3_8

When set, primitive 8 is present in tile 3.

Bits: [24:24]

bool cs_mask_two_byte_tile3_7

When set, primitive 7 is present in tile 3.

Bits: [23:23]

bool cs_mask_two_byte_tile3_6

When set, primitive 6 is present in tile 3.

Bits: [22:22]

bool cs_mask_two_byte_tile3_5

When set, primitive 5 is present in tile 3.

Bits: [21:21]

bool cs_mask_two_byte_tile3_4

When set, primitive 4 is present in tile 3.

Bits: [20:20]

bool cs_mask_two_byte_tile3_3

When set, primitive 3 is present in tile 3.

Bits: [19:19]

bool cs_mask_two_byte_tile3_2

When set, primitive 2 is present in tile 3.

Bits: [18:18]

bool cs_mask_two_byte_tile3_1

When set, primitive 1 is present in tile 3.

Bits: [17:17]

bool cs_mask_two_byte_tile3_0

When set, primitive 0 is present in tile 3.

Bits: [16:16]

bool cs_mask_two_byte_tile2_15

When set, primitive 15 is present in tile 2.

Bits: [15:15]

bool cs_mask_two_byte_tile2_14

When set, primitive 14 is present in tile 2.

Bits: [14:14]

bool cs_mask_two_byte_tile2_13

When set, primitive 13 is present in tile 2.

Bits: [13:13]

bool cs_mask_two_byte_tile2_12

When set, primitive 12 is present in tile 2.

Bits: [12:12]

bool cs_mask_two_byte_tile2_11

When set, primitive 11 is present in tile 2.

Bits: [11:11]

bool cs_mask_two_byte_tile2_10

When set, primitive 10 is present in tile 2.

Bits: [10:10]

bool cs_mask_two_byte_tile2_9

When set, primitive 9 is present in tile 2.

Bits: [9:9]

bool cs_mask_two_byte_tile2_8

When set, primitive 8 is present in tile 2.

Bits: [8:8]

bool cs_mask_two_byte_tile2_7

When set, primitive 7 is present in tile 2.

Bits: [7:7]

bool cs_mask_two_byte_tile2_6

When set, primitive 6 is present in tile 2.

Bits: [6:6]

bool cs_mask_two_byte_tile2_5

When set, primitive 5 is present in tile 2.

Bits: [5:5]

bool cs_mask_two_byte_tile2_4

When set, primitive 4 is present in tile 2.

Bits: [4:4]

bool cs_mask_two_byte_tile2_3

When set, primitive 3 is present in tile 2.

Bits: [3:3]

bool cs_mask_two_byte_tile2_2

When set, primitive 2 is present in tile 2.

Bits: [2:2]

bool cs_mask_two_byte_tile2_1

When set, primitive 1 is present in tile 2.

Bits: [1:1]

bool cs_mask_two_byte_tile2_0

When set, primitive 0 is present in tile 2.

Bits: [0:0]

ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_0_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_0_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_0_SIPF2

Labelling of fields within Byte Based Mask Three-Byte Word 0.

bool cs_mask_three_byte_tile1_7

When set, primitive 1 is present in tile 7.

Bits: [31:31]

bool cs_mask_three_byte_tile1_6

When set, primitive 1 is present in tile 6.

Bits: [30:30]

bool cs_mask_three_byte_tile1_5

When set, primitive 1 is present in tile 5.

Bits: [29:29]

bool cs_mask_three_byte_tile1_4

When set, primitive 1 is present in tile 4.

Bits: [28:28]

bool cs_mask_three_byte_tile1_3

When set, primitive 1 is present in tile 3.

Bits: [27:27]

bool cs_mask_three_byte_tile1_2

When set, primitive 1 is present in tile 2.

Bits: [26:26]

bool cs_mask_three_byte_tile1_1

When set, primitive 1 is present in tile 1.

Bits: [25:25]

bool cs_mask_three_byte_tile1_0

When set, primitive 1 is present in tile 0.

Bits: [24:24]

bool cs_mask_three_byte_tile0_23

When set, primitive 0 is present in tile 23.

Bits: [23:23]

bool cs_mask_three_byte_tile0_22

When set, primitive 0 is present in tile 22.

Bits: [22:22]

bool cs_mask_three_byte_tile0_21

When set, primitive 0 is present in tile 21.

Bits: [21:21]

bool cs_mask_three_byte_tile0_20

When set, primitive 0 is present in tile 20.

Bits: [20:20]

bool cs_mask_three_byte_tile0_19

When set, primitive 0 is present in tile 19.

Bits: [19:19]

bool cs_mask_three_byte_tile0_18

When set, primitive 0 is present in tile 18.

Bits: [18:18]

bool cs_mask_three_byte_tile0_17

When set, primitive 0 is present in tile 17.

Bits: [17:17]

bool cs_mask_three_byte_tile0_16

When set, primitive 0 is present in tile 16.

Bits: [16:16]

bool cs_mask_three_byte_tile0_15

When set, primitive 0 is present in tile 15.

Bits: [15:15]

bool cs_mask_three_byte_tile0_14

When set, primitive 0 is present in tile 14.

Bits: [14:14]

bool cs_mask_three_byte_tile0_13

When set, primitive 0 is present in tile 13.

Bits: [13:13]

bool cs_mask_three_byte_tile0_12

When set, primitive 0 is present in tile 12.

Bits: [12:12]

bool cs_mask_three_byte_tile0_11

When set, primitive 0 is present in tile 11.

Bits: [11:11]

bool cs_mask_three_byte_tile0_10

When set, primitive 0 is present in tile 10.

Bits: [10:10]

bool cs_mask_three_byte_tile0_9

When set, primitive 0 is present in tile 9.

Bits: [9:9]

bool cs_mask_three_byte_tile0_8

When set, primitive 0 is present in tile 8.

Bits: [8:8]

bool cs_mask_three_byte_tile0_7

When set, primitive 0 is present in tile 7.

Bits: [7:7]

bool cs_mask_three_byte_tile0_6

When set, primitive 0 is present in tile 6.

Bits: [6:6]

bool cs_mask_three_byte_tile0_5

When set, primitive 0 is present in tile 5.

Bits: [5:5]

bool cs_mask_three_byte_tile0_4

When set, primitive 0 is present in tile 4.

Bits: [4:4]

bool cs_mask_three_byte_tile0_3

When set, primitive 0 is present in tile 3.

Bits: [3:3]

bool cs_mask_three_byte_tile0_2

When set, primitive 0 is present in tile 2.

Bits: [2:2]

bool cs_mask_three_byte_tile0_1

When set, primitive 0 is present in tile 1.

Bits: [1:1]

bool cs_mask_three_byte_tile0_0

When set, primitive 0 is present in tile 0.

Bits: [0:0]

ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_1_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_1_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_1_SIPF2

Labelling of fields within Byte Based Mask Three-Byte Word 1.

bool cs_mask_three_byte_tile2_15

When set, primitive 15 is present in tile 2.

Bits: [31:31]

bool cs_mask_three_byte_tile2_14

When set, primitive 14 is present in tile 2.

Bits: [30:30]

bool cs_mask_three_byte_tile2_13

When set, primitive 13 is present in tile 2.

Bits: [29:29]

bool cs_mask_three_byte_tile2_12

When set, primitive 12 is present in tile 2.

Bits: [28:28]

bool cs_mask_three_byte_tile2_11

When set, primitive 11 is present in tile 2.

Bits: [27:27]

bool cs_mask_three_byte_tile2_10

When set, primitive 10 is present in tile 2.

Bits: [26:26]

bool cs_mask_three_byte_tile2_9

When set, primitive 9 is present in tile 2.

Bits: [25:25]

bool cs_mask_three_byte_tile2_8

When set, primitive 8 is present in tile 2.

Bits: [24:24]

bool cs_mask_three_byte_tile2_7

When set, primitive 7 is present in tile 2.

Bits: [23:23]

bool cs_mask_three_byte_tile2_6

When set, primitive 6 is present in tile 2.

Bits: [22:22]

bool cs_mask_three_byte_tile2_5

When set, primitive 5 is present in tile 2.

Bits: [21:21]

bool cs_mask_three_byte_tile2_4

When set, primitive 4 is present in tile 2.

Bits: [20:20]

bool cs_mask_three_byte_tile2_3

When set, primitive 3 is present in tile 2.

Bits: [19:19]

bool cs_mask_three_byte_tile2_2

When set, primitive 2 is present in tile 2.

Bits: [18:18]

bool cs_mask_three_byte_tile2_1

When set, primitive 1 is present in tile 2.

Bits: [17:17]

bool cs_mask_three_byte_tile2_0

When set, primitive 0 is present in tile 2.

Bits: [16:16]

bool cs_mask_three_byte_tile1_23

When set, primitive 23 is present in tile 1.

Bits: [15:15]

bool cs_mask_three_byte_tile1_22

When set, primitive 22 is present in tile 1.

Bits: [14:14]

bool cs_mask_three_byte_tile1_21

When set, primitive 21 is present in tile 1.

Bits: [13:13]

bool cs_mask_three_byte_tile1_20

When set, primitive 20 is present in tile 1.

Bits: [12:12]

bool cs_mask_three_byte_tile1_19

When set, primitive 19 is present in tile 1.

Bits: [11:11]

bool cs_mask_three_byte_tile1_18

When set, primitive 18 is present in tile 1.

Bits: [10:10]

bool cs_mask_three_byte_tile1_17

When set, primitive 17 is present in tile 1.

Bits: [9:9]

bool cs_mask_three_byte_tile1_16

When set, primitive 16 is present in tile 1.

Bits: [8:8]

bool cs_mask_three_byte_tile1_15

When set, primitive 15 is present in tile 1.

Bits: [7:7]

bool cs_mask_three_byte_tile1_14

When set, primitive 14 is present in tile 1.

Bits: [6:6]

bool cs_mask_three_byte_tile1_13

When set, primitive 13 is present in tile 1.

Bits: [5:5]

bool cs_mask_three_byte_tile1_12

When set, primitive 12 is present in tile 1.

Bits: [4:4]

bool cs_mask_three_byte_tile1_11

When set, primitive 11 is present in tile 1.

Bits: [3:3]

bool cs_mask_three_byte_tile1_10

When set, primitive 10 is present in tile 1.

Bits: [2:2]

bool cs_mask_three_byte_tile1_9

When set, primitive 9 is present in tile 1.

Bits: [1:1]

bool cs_mask_three_byte_tile1_8

When set, primitive 8 is present in tile 1.

Bits: [0:0]

ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_2_SIPF2_length

Number of 32-bit words used to encode ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_2_SIPF2

struct ROGUE_IPF_BYTE_BASED_MASK_THREE_BYTE_WORD_2_SIPF2

Labelling of fields within Byte Based Mask Three-Byte Word 2.

bool cs_mask_three_byte_tile3_23

When set, primitive 23 is present in tile 3.

Bits: [31:31]

bool cs_mask_three_byte_tile3_22

When set, primitive 22 is present in tile 3.

Bits: [30:30]

bool cs_mask_three_byte_tile3_21

When set, primitive 21 is present in tile 3.

Bits: [29:29]

bool cs_mask_three_byte_tile3_20

When set, primitive 20 is present in tile 3.

Bits: [28:28]

bool cs_mask_three_byte_tile3_19

When set, primitive 19 is present in tile 3.

Bits: [27:27]

bool cs_mask_three_byte_tile3_18

When set, primitive 18 is present in tile 3.

Bits: [26:26]

bool cs_mask_three_byte_tile3_17

When set, primitive 17 is present in tile 3.

Bits: [25:25]

bool cs_mask_three_byte_tile3_16

When set, primitive 16 is present in tile 3.

Bits: [24:24]

bool cs_mask_three_byte_tile3_15

When set, primitive 15 is present in tile 3.

Bits: [23:23]

bool cs_mask_three_byte_tile3_14

When set, primitive 14 is present in tile 3.

Bits: [22:22]

bool cs_mask_three_byte_tile3_13

When set, primitive 13 is present in tile 3.

Bits: [21:21]

bool cs_mask_three_byte_tile3_12

When set, primitive 12 is present in tile 3.

Bits: [20:20]

bool cs_mask_three_byte_tile3_11

When set, primitive 11 is present in tile 3.

Bits: [19:19]

bool cs_mask_three_byte_tile3_10

When set, primitive 10 is present in tile 3.

Bits: [18:18]

bool cs_mask_three_byte_tile3_9

When set, primitive 9 is present in tile 3.

Bits: [17:17]

bool cs_mask_three_byte_tile3_8

When set, primitive 8 is present in tile 3.

Bits: [16:16]

bool cs_mask_three_byte_tile3_7

When set, primitive 7 is present in tile 3.

Bits: [15:15]

bool cs_mask_three_byte_tile3_6

When set, primitive 6 is present in tile 3.

Bits: [14:14]

bool cs_mask_three_byte_tile3_5

When set, primitive 5 is present in tile 3.

Bits: [13:13]

bool cs_mask_three_byte_tile3_4

When set, primitive 4 is present in tile 3.

Bits: [12:12]

bool cs_mask_three_byte_tile3_3

When set, primitive 3 is present in tile 3.

Bits: [11:11]

bool cs_mask_three_byte_tile3_2

When set, primitive 2 is present in tile 3.

Bits: [10:10]

bool cs_mask_three_byte_tile3_1

When set, primitive 1 is present in tile 3.

Bits: [9:9]

bool cs_mask_three_byte_tile3_0

When set, primitive 0 is present in tile 3.

Bits: [8:8]

bool cs_mask_three_byte_tile2_23

When set, primitive 23 is present in tile 2.

Bits: [7:7]

bool cs_mask_three_byte_tile2_22

When set, primitive 22 is present in tile 2.

Bits: [6:6]

bool cs_mask_three_byte_tile2_21

When set, primitive 21 is present in tile 2.

Bits: [5:5]

bool cs_mask_three_byte_tile2_20

When set, primitive 20 is present in tile 2.

Bits: [4:4]

bool cs_mask_three_byte_tile2_19

When set, primitive 19 is present in tile 2.

Bits: [3:3]

bool cs_mask_three_byte_tile2_18

When set, primitive 18 is present in tile 2.

Bits: [2:2]

bool cs_mask_three_byte_tile2_17

When set, primitive 17 is present in tile 2.

Bits: [1:1]

bool cs_mask_three_byte_tile2_16

When set, primitive 16 is present in tile 2.

Bits: [0:0]

ROGUE_IPF_COMPRESSION_SIZE_WORD_length

Number of 32-bit words used to encode ROGUE_IPF_COMPRESSION_SIZE_WORD

struct ROGUE_IPF_COMPRESSION_SIZE_WORD

Labelling of fields within Compression Size Word.

uint32_t cs_isp_comp_table_size

Total ISP Compression Table Size in bytes.

Bits: [27:31]

uint32_t cs_tsp_comp_format_size

Data size in DWords for compression format data of TSP vertex data including RHW and all the texture coordinate sets if present.

Bits: [21:26]

uint32_t cs_tsp_comp_table_size

Total TSP Compression Table Size in bytes.

Bits: [9:18]

uint32_t cs_tsp_comp_vertex_size

Size of a Compressed TSP Vertex in bytes.

Bits: [0:8]

ROGUE_IPF_ISP_COMPRESSION_WORD_0_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_COMPRESSION_WORD_0

struct ROGUE_IPF_ISP_COMPRESSION_WORD_0

Labelling of fields within ISP Compression Word 0.

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_z1

ISP Compression Format.

Bits: [28:31]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_z0

ISP Compression Format.

Bits: [24:27]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_y2

ISP Compression Format.

Bits: [20:23]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_y1

ISP Compression Format.

Bits: [16:19]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_y0

ISP Compression Format.

Bits: [12:15]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_x2

ISP Compression Format.

Bits: [8:11]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_x1

ISP Compression Format.

Bits: [4:7]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_x0

ISP Compression Format.

Bits: [0:3]

ROGUE_IPF_ISP_COMPRESSION_WORD_1_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_COMPRESSION_WORD_1

struct ROGUE_IPF_ISP_COMPRESSION_WORD_1

Labelling of fields within ISP Compression Word 1.

bool vf_prim_msaa

If set, MSAA is enabled in this primitive block.

Bits: [16:16]

bool vf_prim_id_pres

If set, primitive ID words are present in this primitive block.

Bits: [15:15]

bool vf_vertex_clipped

If set, TSP Vertex data has been generated by the clipper.

Bits: [14:14]

uint32_t vf_vertex_total

The number of vertices in the primitive block minus, i.e. 0 mean 1 vertex.

Bits: [8:13]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_z3

ISP Compression Format.

Bits: [4:7]

enum ROGUE_IPF_COMPRESSION_FORMAT cf_isp_comp_fmt_z2

ISP Compression Format.

Bits: [0:3]

ROGUE_IPF_INDEX_DATA_length

Number of 32-bit words used to encode ROGUE_IPF_INDEX_DATA

struct ROGUE_IPF_INDEX_DATA

Labelling of fields within Index Data.

bool ix_edge_flag1_ab

Visibility flag for edge AB for triangle 1.

Bits: [30:30]

uint32_t ix_index1_0

Vertex A of triangle 1.

Bits: [24:29]

bool ix_bf_flag0

If set, triangle 0 is back face.

Bits: [23:23]

bool ix_edge_flag0_ca

Visibility flag for edge CA for triangle 0.

Bits: [22:22]

uint32_t ix_index0_2

Vertex C of triangle 0.

Bits: [16:21]

bool ix_edge_flag0_bc

Visibility flag for edge BC for triangle 0.

Bits: [14:14]

uint32_t ix_index0_1

Vertex B of triangle 0.

Bits: [8:13]

bool ix_edge_flag0_ab

Visibility flag for edge AB for triangle 0.

Bits: [6:6]

uint32_t ix_index0_0

Vertex A of triangle 0.

Bits: [0:5]

ROGUE_IPF_ISP_VERTEX_XY_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_XY

struct ROGUE_IPF_ISP_VERTEX_XY

Labelling of fields within ISP Vertex X and Y coordinates, raw encoding.

bool sign

Bits: [23:23]

uint32_t integer

Bits: [8:22]

uint32_t frac

Bits: [0:7]

ROGUE_IPF_ISP_VERTEX_XY_SIPF_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_XY_SIPF

struct ROGUE_IPF_ISP_VERTEX_XY_SIPF

Labelling of fields within ISP Vertex X and Y coordinates, raw encoding.

uint32_t integer

Bits: [4:16]

uint32_t frac

Bits: [0:3]

ROGUE_IPF_ISP_VERTEX_WORD_SIPF_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_SIPF

struct ROGUE_IPF_ISP_VERTEX_WORD_SIPF

Labelling of fields within ISP Vertex Word, raw encoding.

uint32_t z

Z floating-point value.

Bits: [34:63]

uint32_t y

Y fixed-point value.

Bits: [17:33]

uint32_t x

X fixed-point value.

Bits: [0:16]

ROGUE_IPF_ISP_VERTEX_WORD_0_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_0

struct ROGUE_IPF_ISP_VERTEX_WORD_0

Labelling of fields within ISP Vertex Word 0, raw encoding.

uint32_t y0

Y0 fixed-point value, least-significant 1 byte.

Bits: [24:31]

uint32_t x0

X0 fixed-point value.

Bits: [0:23]

ROGUE_IPF_ISP_VERTEX_WORD_1_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_1

struct ROGUE_IPF_ISP_VERTEX_WORD_1

Labelling of fields within ISP Vertex Word 1, raw encoding.

uint32_t z0

Z0 floating-point value, least-significant 2 bytes.

Bits: [16:31]

uint32_t y0

Y0 fixed-point value, most-significant 2 bytes.

Bits: [0:15]

ROGUE_IPF_ISP_VERTEX_WORD_2_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_2

struct ROGUE_IPF_ISP_VERTEX_WORD_2

Labelling of fields within ISP Vertex Word 2, raw encoding.

uint32_t x1

X1 fixed-point value, least-significant 2 bytes.

Bits: [16:31]

uint32_t z0

Z0 floating-point value, most-significant 2 bytes.

Bits: [0:15]

ROGUE_IPF_ISP_VERTEX_WORD_3_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_3

struct ROGUE_IPF_ISP_VERTEX_WORD_3

Labelling of fields within ISP Vertex Word 3, raw encoding.

uint32_t y1

Y1 fixed-point value.

Bits: [8:31]

uint32_t x1

X1 fixed-point value, most-significant 1 byte.

Bits: [0:7]

ROGUE_IPF_ISP_VERTEX_WORD_4_length

Number of 32-bit words used to encode ROGUE_IPF_ISP_VERTEX_WORD_4

struct ROGUE_IPF_ISP_VERTEX_WORD_4

Labelling of fields within ISP Vertex Word 4, raw encoding.

uint32_t z1

Z1 floating-point value.

Bits: [0:31]

LLS (Low-Latency Scheduling)

API documentation for Low-Latency Scheduling defines:

ROGUE_LLS_CDM_CONTEXT_RESUME_BUFFER_ALIGNMENT

Alignment of the CDM’s context state buffer in bytes.

ROGUE_LLS_CDM_CONTEXT_RESUME_BUFFER_SIZE

Size of the CDM’s context state buffer in bytes.

ROGUE_LLS_PDS_PERSISTENT_TEMPS_BUFFER_ALIGNMENT

Alignment of the PDS’s persistent-temporary register context state buffer in bytes.

ROGUE_LLS_PDS_PERSISTENT_TEMPS_BUFFER_SIZE

Size of the PDS’s persistent-temporary register context state buffer in bytes.

ROGUE_LLS_TA_STATE_BUFFER_ALIGNMENT

Alignment of the TA’s context state buffer in bytes.

ROGUE_LLS_TA_STATE_BUFFER_SIZE

Size of the TA’s context state buffer in bytes.

ROGUE_LLS_USC_SHARED_REGS_BUFFER_ALIGNMENT

Alignment of the USC’s shared register context state buffer in bytes.

ROGUE_LLS_USC_SHARED_REGS_BUFFER_SIZE

Size of the USC’s shared register context state buffer in bytes.

ROGUE_LLS_VDM_CONTEXT_RESUME_BUFFER_ALIGNMENT

Alignment of the VDM’s context resume control stream buffer in bytes.

ROGUE_LLS_VDM_CONTEXT_RESUME_BUFFER_SIZE

Size of the VDM’s context resume control stream buffer in bytes.

PBESTATE (Pixel Backend State)

API documentation for Pixel Backend structures and functions:

enum ROGUE_PBESTATE_COMP_IADDR_TYPE

Compressor indirect addressing mode.

enum ROGUE_PBESTATE_COMPRESS_SIZE

Compressor block size.

enum ROGUE_PBESTATE_COMPRESS_SIZE_EXT

Compressor block size extension bit.

enum ROGUE_PBESTATE_COMPRESSION

Sets the frame buffer compression.

enum ROGUE_PBESTATE_LOSSY

Sets the lossy bit for frame buffer compression.

enum ROGUE_PBESTATE_MEMLAYOUT

Sets the memory layout.

enum ROGUE_PBESTATE_PACKMODE

Sets the memory layout.

enumerator ROGUE_PBESTATE_PACKMODE_U8U8U8 = 18

24-bit packed.

enumerator ROGUE_PBESTATE_PACKMODE_S8S8S8 = 19

24-bit packed.

enumerator ROGUE_PBESTATE_PACKMODE_PBYTE = 55

Order of packed bytes. Indicated by ROTMODE and MEML.

enumerator ROGUE_PBESTATE_PACKMODE_PWORD = 56

Order of packed (16-bit) words. Indicated by ROTMODE and MEML.

enumerator ROGUE_PBESTATE_PACKMODE_A2_XRBIAS_U10U10U10 = 58

Same as the DX XRBIAS packmode BUT A[1:0] == ‘11’b should be set always.

enumerator ROGUE_PBESTATE_PACKMODE_YUV = 59

YUV placeholder pointing to the YUV_PMODE.

enumerator ROGUE_PBESTATE_PACKMODE_U10U10U10_XRBIAS_A2 = 60

Same as the DX XRBIAS packmode BUT A[1:0] == ‘11’b should be set always.

enum ROGUE_PBESTATE_PAIR_TILES

Enables tile pairing.

enum ROGUE_PBESTATE_ROTATION_TYPE

Sets the rotation.

enum ROGUE_PBESTATE_SIZE

Size of twiddled render in pixel units.

enum ROGUE_PBESTATE_SOURCE_FORMAT

Indicates USC output buffer packing. Not needed for F32 source format since the F32 packing mode automatically implies that the source format is F32 as well.

enumerator ROGUE_PBESTATE_SOURCE_FORMAT_F16_PER_CHANNEL = 0

Only needed for F16 source format where the packing mode is equal to or less than 16-bits.

enumerator ROGUE_PBESTATE_SOURCE_FORMAT_8_PER_CHANNEL = 1

Only for 8-bits source formats where the packing mode is equal to or less than 8-bits.

enum ROGUE_PBESTATE_SOURCE_POS

Start position in source buffer.

enum ROGUE_PBESTATE_SWIZ

Sets the swizzle.

enumerator ROGUE_PBESTATE_SWIZ_SOURCE_CHAN0 = 0

Indicates source channel0 goes to this destination channel.

enumerator ROGUE_PBESTATE_SWIZ_SOURCE_CHAN1 = 1

Indicates source channel1 goes to this destination channel.

enumerator ROGUE_PBESTATE_SWIZ_SOURCE_CHAN2 = 2

Indicates source channel2 goes to this destination channel.

enumerator ROGUE_PBESTATE_SWIZ_SOURCE_CHAN3 = 3

Indicates source channel3 goes to this destination channel.

enumerator ROGUE_PBESTATE_SWIZ_ONE = 4

Send a value of 1 to this destination channel.

enumerator ROGUE_PBESTATE_SWIZ_ZERO = 5

Send a value of 0 to this destination channel.

enum ROGUE_PBESTATE_TFBC_LOSSY

Sets the lossy bits for frame buffer compression.

enumerator ROGUE_PBESTATE_TFBC_LOSSY_LOSSLESS = 0

Lossless compression.

enumerator ROGUE_PBESTATE_TFBC_LOSSY_LOSSY75 = 1

Lossy compression down to 75% of the original size.

enumerator ROGUE_PBESTATE_TFBC_LOSSY_LOSSY50 = 2

Lossy compression down to 50% of the original size.

enumerator ROGUE_PBESTATE_TFBC_LOSSY_LOSSY25 = 3

Lossy compression down to 25% of the original size.

enum ROGUE_PBESTATE_TWOCOMP_GAMMA

Sets the gamma mode for 2 component textures.

enum ROGUE_PBESTATE_Y_FLIP

Enables Y Flipping.

enum ROGUE_PBESTATE_YUV_DOWNSCALE

Sets the YUV downscale.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_NO_DOWNSCALING = 0

No downscale applied.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_ONE_SAMPLE_LEFT = 1

Cosited for 422 & 420, selects src0.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_EMPTY = 2

Empty definition, for future use.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_TWO_SAMPLES = 3

Centered for 422, Horizontally Centered & Vertically Cosited for 420, results to (src0+src1)/2.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_FOUR_SAMPLES = 4

Centered for 420, results to (src0+src1+src2+src3)/4.

enumerator ROGUE_PBESTATE_YUV_DOWNSCALE_ONE_SAMPLE_RIGHT = 5

Cosited for 422 & 420, selects src1.

enum ROGUE_PBESTATE_YUV_PMODE

Defines new YUV packmodes.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV8_420_2PLANE = 0

8-bit UV components from a YUV420 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_U8_420_3PLANE = 1

8-bit U component from a YUV420 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_V8_420_3PLANE = 2

8-bit V component from a YUV420 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_YUV8_422_1PLANE = 3

8-bit YUV components from a YUV422 1 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV8_422_2PLANE = 4

8-bit UV components from a YUV422 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV8_444_2PLANE = 5

8-bit UV components from a YUV444 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_Y8_23PLANE = 6

8-bit Y component from a YUV444/422/420 2/3 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_U8_444_3PLANE = 7

8-bit U component from a YUV444 3 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_V8_444_3PLANE = 8

8-bit V component from a YUV444 3 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_YUV10_444_1PLANE = 9

10-bit YUV components from a YUV444 1 Plane format, packed in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_RESERVED_YUV1 = 10

Reserved for future YUV packmodes.

enumerator ROGUE_PBESTATE_YUV_PMODE_RESERVED_YUV2 = 11

Reserved for future YUV packmodes.

enumerator ROGUE_PBESTATE_YUV_PMODE_YUV10_422_1PLANE = 12

10-bit packed YUV components from a YUV422 1 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV10_420_2PLANE = 13

10-bit packed UV components from a YUV420 2 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_Y10_23PLANE = 14

10-bit packed Y component from a YUV444/422/420 2/3 Plane format.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV16_420_2PLANE = 15

10-bit UV components from a YUV420 2 Plane format, packed as 16-bits in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV16_422_2PLANE = 16

10-bit UV components from a YUV422 2 Plane format, packed as 16-bits in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_UV16_444_2PLANE = 17

10-bit UV components from a YUV444 2 Plane format, packed as 16-bits in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_Y16_23PLANE = 18

10-bit Y component from a YUV444/422/420 2/3 Plane format, packed as 16-bits in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_U16_444_3PLANE = 19

10-bit U component from a YUV444 3 Plane format, packed as 16-bits in 32-bit word.

enumerator ROGUE_PBESTATE_YUV_PMODE_V16_444_3PLANE = 20

10-bit V component from a YUV444 3 Plane format, packed as 16-bits in 32-bit word.

ROGUE_PBESTATE_STATE_WORD0_length

Number of 32-bit words used to encode ROGUE_PBESTATE_STATE_WORD0

ROGUE_PBESTATE_STATE_WORD1_length

Number of 32-bit words used to encode ROGUE_PBESTATE_STATE_WORD1

ROGUE_PBESTATE_REG_WORD0_length

Number of 32-bit words used to encode ROGUE_PBESTATE_REG_WORD0

ROGUE_PBESTATE_REG_WORD1_length

Number of 32-bit words used to encode ROGUE_PBESTATE_REG_WORD1

ROGUE_PBESTATE_REG_WORD2_length

Number of 32-bit words used to encode ROGUE_PBESTATE_REG_WORD2

PDS (Programmable Data Sequencer)

API documentation for Programmable Data Sequencer structures and functions:

enum ROGUE_PDSINST_CMODE_LD

MCU (SLC) Cache Mode for Loads.

enumerator ROGUE_PDSINST_CMODE_LD_CACHED = 0

Normal cache operation.

enumerator ROGUE_PDSINST_CMODE_LD_BYPASS = 1

Bypass L0 and L1.

enumerator ROGUE_PDSINST_CMODE_LD_FORCE_LINE_FILL = 2

Force line fill of L0 and L1.

enum ROGUE_PDSINST_DOUTI_SHADEMODEL

Shade Model Control.

enumerator ROGUE_PDSINST_DOUTI_SHADEMODEL_FLAT_VERTEX0 = 0

Vertex 0 is the flat shaded colour source.

enumerator ROGUE_PDSINST_DOUTI_SHADEMODEL_FLAT_VERTEX1 = 1

Vertex 1 is the flat shaded colour source.

enumerator ROGUE_PDSINST_DOUTI_SHADEMODEL_FLAT_VERTEX2 = 2

Vertex 2 is the flat shaded colour source.

enumerator ROGUE_PDSINST_DOUTI_SHADEMODEL_GOURUAD = 3

Gouraud shaded.

enum ROGUE_PDSINST_DOUTU_SAMPLE_RATE

Sample rate.

enumerator ROGUE_PDSINST_DOUTU_SAMPLE_RATE_INSTANCE = 0

Instance rate.

enumerator ROGUE_PDSINST_DOUTU_SAMPLE_RATE_SELECTIVE = 1

Selective sample rate.

enumerator ROGUE_PDSINST_DOUTU_SAMPLE_RATE_FULL = 2

Full sample rate.

enum ROGUE_PDSINST_SLC_MODE_LD

SLC Cache Policy for loads.

enumerator ROGUE_PDSINST_SLC_MODE_LD_BYPASS = 0

Bypass Policy.

enumerator ROGUE_PDSINST_SLC_MODE_LD_CACHED = 1

Standard Cached Read.

enumerator ROGUE_PDSINST_SLC_MODE_LD_CACHED_RD_NA = 3

Cached Read no allocate.

enum ROGUE_PDSINST_WORDSIZE

When repeat is enabled the size of the DMA in bytes.

enumerator ROGUE_PDSINST_WORDSIZE_ONE = 0

DMA of 1 byte.

enumerator ROGUE_PDSINST_WORDSIZE_TWO = 1

DMA of 2 bytes.

enumerator ROGUE_PDSINST_WORDSIZE_THREE = 2

DMA of 3 bytes.

enumerator ROGUE_PDSINST_WORDSIZE_FOUR = 3

DMA of 4 bytes.

ROGUE_PDSINST_DDMAD_FIELDS_SRC3_length

Number of 32-bit words used to encode ROGUE_PDSINST_DDMAD_FIELDS_SRC3

ROGUE_PDSINST_DOUTU_SRC0_length

Number of 32-bit words used to encode ROGUE_PDSINST_DOUTU_SRC0

struct ROGUE_PDSINST_DOUTU_SRC0

Use Interface DOutU : Src0.

bool dual_phase

Bits: [41:41]

uint32_t temps

Bits: [35:40]

enum ROGUE_PDSINST_DOUTU_SAMPLE_RATE sample_rate

Bits: [33:34]

uint64_t exe_off

Bits: [2:31]

ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0_length

Number of 32-bit words used to encode ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0

struct ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC0

DMA Interface DOutD : Src0.

enum ROGUE_PDSINST_SLC_MODE_LD slcmode

SLC cache policy.

Bits: [60:61]

uint32_t doffset

Secondary instance data offset in 32-bit words (offset of the instance).

Bits: [40:52]

uint64_t sbase

Source Base Address for memory fetch.

Bits: [0:39]

ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1_length

Number of 32-bit words used to encode ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1

struct ROGUE_PDSINST_DOUT_FIELDS_DOUTD_SRC1

DMA Interface DOutD : Src1.

bool last

Last Write or DMA in program (This needs to only be set once on with the last DMA or last direct write, which ever is last).

Bits: [31:31]

enum ROGUE_PDSINST_WORDSIZE wordsize

Bits: [29:30]

enum ROGUE_PDSINST_DOUTD_DEST dest

Bits: [28:28]

enum ROGUE_PDSINST_CMODE_LD cmode

Cache Mode.

Bits: [26:27]

uint32_t a0

Primary instance data offset in 32-bit words (offset into the current instance).

Bits: [13:25]

bool repeat

Bits: [12:12]

uint32_t bsize

Size of fetch in DWords (0 means don’t DMA, 1=1 etc.).

Bits: [0:11]

ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC_length

Number of 32-bit words used to encode ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC

struct ROGUE_PDSINST_DOUT_FIELDS_DOUTI_SRC

TSP Parameter Fetch Interface DOutI, This command is only legal in a coefficient loading program.

bool depthbias

Apply depth bias to this layer.

Bits: [27:27]

bool primitiveid

Ignore the F16 and F32 offsets, and the WMODE and send the primitive ID instead.

Bits: [26:26]

enum ROGUE_PDSINST_DOUTI_SHADEMODEL shademodel

Shade Model for Layer.

Bits: [24:25]

bool pointsprite

Point sprite Forced.

Bits: [23:23]

bool wraps

Wrap S Coordinate.

Bits: [22:22]

bool wrapv

Wrap V Coordinate.

Bits: [21:21]

bool wrapu

Wrap U Coordinate.

Bits: [20:20]

enum ROGUE_PDSINST_DOUTI_SIZE size

Bits: [18:19]

bool f16

Issue is for F16 precision values.

Bits: [17:17]

bool perspective

Bits: [16:16]

uint32_t f32_offset

The offset within the vertex if all data is treated as F32 (even if submitted as F16).

Bits: [8:15]

uint32_t f16_offset

The offset within vertex taking into account the F16s and F32s present.

Bits: [0:7]

PPP (Primitive Processing Pipeline)

API documentation for Primitive Processing Pipeline structures and functions:

enum ROGUE_TA_CMPMODE

Compare mode used in performing depth/stencil tests.

enum ROGUE_TA_CULLMODE

Selects the back face culling mode.

enum ROGUE_TA_FLATSHADE

Indicates which vertex to use as the source when flat shading.

enum ROGUE_TA_GS_OUTPUT_TOPOLOGY

Specifies the output primitive topology from the Geometry Shader.

enum ROGUE_TA_PASSTYPE

Identifies the ISP pass type.

enumerator ROGUE_TA_PASSTYPE_DEPTH_FEEDBACK = 5

Assume always alpha tested.

enumerator ROGUE_TA_PASSTYPE_ANTI_ALIASED = 6

Order dependent.

enum ROGUE_TA_REGION_CLIP_MODE

TA region based clip condition.

ROGUE_TA_STATE_HEADER_length

Number of 32-bit words used to encode ROGUE_TA_STATE_HEADER

ROGUE_TA_STATE_ISPCTL_length

Number of 32-bit words used to encode ROGUE_TA_STATE_ISPCTL

ROGUE_TA_STATE_ISPA_length

Number of 32-bit words used to encode ROGUE_TA_STATE_ISPA

ROGUE_TA_STATE_ISPB_length

Number of 32-bit words used to encode ROGUE_TA_STATE_ISPB

ROGUE_TA_REGION_CLIP0_length

Number of 32-bit words used to encode ROGUE_TA_REGION_CLIP0

ROGUE_TA_REGION_CLIP1_length

Number of 32-bit words used to encode ROGUE_TA_REGION_CLIP1

ROGUE_TA_WCLAMP_length

Number of 32-bit words used to encode ROGUE_TA_WCLAMP

ROGUE_TA_STATE_ISPDBSC_length

Number of 32-bit words used to encode ROGUE_TA_STATE_ISPDBSC

ROGUE_TA_OUTPUT_SEL_length

Number of 32-bit words used to encode ROGUE_TA_OUTPUT_SEL

ROGUE_TA_STATE_VARYING0_length

Number of 32-bit words used to encode ROGUE_TA_STATE_VARYING0

ROGUE_TA_STATE_VARYING1_length

Number of 32-bit words used to encode ROGUE_TA_STATE_VARYING1

ROGUE_TA_STATE_VARYING2_length

Number of 32-bit words used to encode ROGUE_TA_STATE_VARYING2

ROGUE_TA_STATE_TERMINATE0_length

Number of 32-bit words used to encode ROGUE_TA_STATE_TERMINATE0

ROGUE_TA_STATE_TERMINATE1_length

Number of 32-bit words used to encode ROGUE_TA_STATE_TERMINATE1

ROGUE_TA_STATE_STREAM_OUT0_length

Number of 32-bit words used to encode ROGUE_TA_STATE_STREAM_OUT0

ROGUE_TA_STATE_STREAM_OUT1_length

Number of 32-bit words used to encode ROGUE_TA_STATE_STREAM_OUT1

ROGUE_TA_STATE_STREAM_OUT2_length

Number of 32-bit words used to encode ROGUE_TA_STATE_STREAM_OUT2

ROGUE_TA_STATE_PDS_SHADERBASE_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_SHADERBASE

struct ROGUE_TA_STATE_PDS_SHADERBASE

The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only.

uint64_t addr

Bits: [4:31]

ROGUE_TA_STATE_PDS_TEXUNICODEBASE_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_TEXUNICODEBASE

struct ROGUE_TA_STATE_PDS_TEXUNICODEBASE

This is the PDS Code Address used for 2 programs. The Program which issues the DMAs (DOUTD etc.) for uniform data and/or texture state.

uint64_t addr

Bits: [4:31]

ROGUE_TA_STATE_PDS_VARYINGBASE_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_VARYINGBASE

struct ROGUE_TA_STATE_PDS_VARYINGBASE

This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE.

uint64_t addr

Bits: [4:31]

ROGUE_TA_STATE_PDS_TEXTUREDATABASE_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_TEXTUREDATABASE

struct ROGUE_TA_STATE_PDS_TEXTUREDATABASE

This points to the DMAs to load the Texture State (or contains the State with DOUTW commands).

uint64_t addr

Bits: [4:31]

ROGUE_TA_STATE_PDS_UNIFORMDATABASE_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_UNIFORMDATABASE

struct ROGUE_TA_STATE_PDS_UNIFORMDATABASE

This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands).

uint64_t addr

Bits: [4:31]

ROGUE_TA_STATE_PDS_SIZEINFO1_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_SIZEINFO1

struct ROGUE_TA_STATE_PDS_SIZEINFO1

If any of the size fields are 0, then that program will not be run. PDS_PIXELSHADERSIZE is always 2 128-bit Words.

uint32_t pds_uniformsize

Bits: [23:31]

uint32_t pds_texturestatesize

Bits: [16:22]

uint32_t pds_varyingsize

Bits: [10:15]

uint32_t usc_varyingsize

Bits: [4:9]

uint32_t pds_tempsize

0 = 16 128-bit words, 1 = 1 128-bit word.

Bits: [0:3]

ROGUE_TA_STATE_PDS_SIZEINFO2_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PDS_SIZEINFO2

struct ROGUE_TA_STATE_PDS_SIZEINFO2

If any of the size fields are 0, then that program will not be run.

uint32_t usc_sharedsize

Bits: [23:31]

bool pds_tri_merge_disable

Disable triangle merging.

Bits: [14:14]

uint32_t pds_batchnum

Bits: [0:13]

ROGUE_TA_STATE_PPP_CTRL_length

Number of 32-bit words used to encode ROGUE_TA_STATE_PPP_CTRL

TEXSTATE (Texture State)

API documentation for Texture State structures and functions:

enum ROGUE_TEXSTATE_ADDRMODE

Specifies texture address mode.

enum ROGUE_TEXSTATE_ANISOCTL

Specifies maximum anisotropy.

enumerator ROGUE_TEXSTATE_ANISOCTL_DISABLED = 0

No Aniso.

enumerator ROGUE_TEXSTATE_ANISOCTL_X2 = 1

Aniso X2.

enumerator ROGUE_TEXSTATE_ANISOCTL_X4 = 2

Aniso X4.

enumerator ROGUE_TEXSTATE_ANISOCTL_X8 = 3

Aniso X8.

enumerator ROGUE_TEXSTATE_ANISOCTL_X16 = 4

Aniso X16.

enum ROGUE_TEXSTATE_CLAMP

Sets the min/max clamp on LOD. 4.6 number format.

enumerator ROGUE_TEXSTATE_CLAMP_MIN = 0

Represents 0.

enumerator ROGUE_TEXSTATE_CLAMP_MAX = 959

Represents 14.984375.

enum ROGUE_TEXSTATE_CMP_MODE

Specifies comparison modes.

enumerator ROGUE_TEXSTATE_CMP_MODE_NEVER = 0

Never, always return 0.

enumerator ROGUE_TEXSTATE_CMP_MODE_LESS = 1

Less than, Ref < TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_EQUAL = 2

Equal to, Ref = TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_LESSEQUAL = 3

Less or equal to, Ref <= TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_GREATER = 4

Greater than, Ref > TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_NOTEQUAL = 5

Not equal to, Ref != TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_GREATEREQUAL = 6

Greater or equal to, Ref >= TexelData.

enumerator ROGUE_TEXSTATE_CMP_MODE_ALWAYS = 7

Always, always return 1.

enum ROGUE_TEXSTATE_COMPRESSION_LEVEL

Sets the lossy compression level for TFBC.

enumerator ROGUE_TEXSTATE_COMPRESSION_LEVEL_LOSSLESS = 0

Lossless compression.

enumerator ROGUE_TEXSTATE_COMPRESSION_LEVEL_LOSSY_75 = 1

Lossy compression down to 75% of the original size (lowest compression ratio).

enumerator ROGUE_TEXSTATE_COMPRESSION_LEVEL_LOSSY_50 = 2

Lossy compression down to 50% of the original size.

enumerator ROGUE_TEXSTATE_COMPRESSION_LEVEL_LOSSY_25 = 3

Lossy compression down to 25% of the original size (highest compression ratio).

enum ROGUE_TEXSTATE_COMPRESSION_MODE

Sets the compression mode.

enum ROGUE_TEXSTATE_DADJUST

Sets the range of the DADJUST (aka LOD Bias). 5.8 number format.

enumerator ROGUE_TEXSTATE_DADJUST_MIN_UINT = 0

Represents -15.996.

enumerator ROGUE_TEXSTATE_DADJUST_ZERO_UINT = 4095

Represents 0.0.

enumerator ROGUE_TEXSTATE_DADJUST_MAX_UINT = 8191

Represents 16.0.

enum ROGUE_TEXSTATE_FILTER

Specifies texture filter.

enumerator ROGUE_TEXSTATE_FILTER_POINT = 0

Point filter.

enumerator ROGUE_TEXSTATE_FILTER_LINEAR = 1

Bilinear filter.

enumerator ROGUE_TEXSTATE_FILTER_BICUBIC = 2

Bicubic filter.

enum ROGUE_TEXSTATE_FORMAT

Sets the texture format.

enum ROGUE_TEXSTATE_FORMAT_COMPRESSED

Sets the texture format.

enum ROGUE_TEXSTATE_GAMMA

Sets the gamma mode.

enum ROGUE_TEXSTATE_SWIZ

Sets the swizzle.

enum ROGUE_TEXSTATE_TEXTYPE

Sets the texture type.

enum ROGUE_TEXSTATE_TWOCOMP_GAMMA

Sets the gamma mode for 2 component textures.

enum ROGUE_TEXSTATE_CHROMAINTERP

Sets the Chroma interpolation.

ROGUE_TEXSTATE_IMAGE_WORD0_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_IMAGE_WORD0

ROGUE_TEXSTATE_IMAGE_WORD1_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_IMAGE_WORD1

ROGUE_TEXSTATE_STRIDE_IMAGE_WORD1_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_STRIDE_IMAGE_WORD1

ROGUE_TEXSTATE_YUV_IMAGE_WORD1_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_YUV_IMAGE_WORD1

ROGUE_TEXSTATE_SAMPLER_WORD0_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_SAMPLER_WORD0

ROGUE_TEXSTATE_SAMPLER_WORD1_length

Number of 32-bit words used to encode ROGUE_TEXSTATE_SAMPLER_WORD1

VDM (Vertex Data Master)

API documentation for Vertex Data Master structures and functions:

ROGUE_VDMCTRL_GUARD_SIZE_DEFAULT

The driver must not put any STREAM_LINK, STREAM_RETURN or STREAM_TERMINATE blocks in the final GUARD_SIZE bytes of the last valid page.

enum ROGUE_VDMCTRL_BLOCK_TYPE

The VDM control stream block header type.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_PPP_STATE_UPDATE = 0

PPP State Update.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_PDS_STATE_UPDATE = 1

PDS State Update.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_VDM_STATE_UPDATE = 2

VDM State Update.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_INDEX_LIST = 3

Index List.

Stream Link.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_RETURN = 5

Stream Return.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_STREAM_TERMINATE = 6

Stream Terminate.

enumerator ROGUE_VDMCTRL_BLOCK_TYPE_CONTROL = 7

Control.

enum ROGUE_VDMCTRL_FLATSHADE_CONTROL

Indicates which vertex of the triangle contains the flat shaded colour source. It is only required for triangle strips which contain flat shaded data.

enumerator ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_0 = 0

Vertex 0 contains the flat shaded colour source.

enumerator ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_1 = 1

Vertex 1 contains the flat shaded colour source.

enumerator ROGUE_VDMCTRL_FLATSHADE_CONTROL_VERTEX_2 = 2

Vertex 2 contains the flat shaded colour source.

enum ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT

Selects how much extra space to allocate in the UVS per vertex.

enumerator ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT_FIVE = 0

Allocate an extra 1 DWord.

enumerator ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT_ONE = 1

Allocate an extra 5 DWords.

ROGUE_VDMCTRL_PPP_STATE0_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_PPP_STATE0

ROGUE_VDMCTRL_PPP_STATE1_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_PPP_STATE1

ROGUE_VDMCTRL_PDS_STATE0_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_PDS_STATE0

ROGUE_VDMCTRL_PDS_STATE1_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_PDS_STATE1

ROGUE_VDMCTRL_PDS_STATE2_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_PDS_STATE2

ROGUE_VDMCTRL_STREAM_LINK0_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_STREAM_LINK0

struct ROGUE_VDMCTRL_STREAM_LINK0

Stream Link.

enum ROGUE_VDMCTRL_BLOCK_TYPE block_type

Stream Link header.

Bits: [29:31] Default: STREAM_LINK

bool with_return

If set, stream at ADDR must end with a return, not terminate.

Bits: [28:28]

bool compare_present

Enable conditional linking, and words 2 & 3 are present. If condition passes, link is followed.

Bits: [27:27]

uint32_t compare_mode

Compare mode.

Bits: [24:26]

uint32_t compare_data

Reference value to compare against.

Bits: [8:23]

MSB of Stream link address.

Bits: [0:7]

ROGUE_VDMCTRL_STREAM_LINK1_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_STREAM_LINK1

ROGUE_VDMCTRL_STREAM_RETURN_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_STREAM_RETURN

struct ROGUE_VDMCTRL_STREAM_RETURN

VDM Stream Return.

enum ROGUE_VDMCTRL_BLOCK_TYPE block_type

Bits: [29:31] Default: STREAM_RETURN

ROGUE_VDMCTRL_STREAM_TERMINATE_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_STREAM_TERMINATE

struct ROGUE_VDMCTRL_STREAM_TERMINATE

VDM Stream Terminate.

enum ROGUE_VDMCTRL_BLOCK_TYPE block_type

Bits: [29:31] Default: STREAM_TERMINATE

bool context

Indicates that the terminate is a context store terminate. Only set by HW.

Bits: [0:0]

ROGUE_VDMCTRL_VDM_STATE0_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE0

struct ROGUE_VDMCTRL_VDM_STATE0

VDM State update first word.

enum ROGUE_VDMCTRL_BLOCK_TYPE block_type

VDM State update header.

Bits: [29:31] Default: VDM_STATE_UPDATE

bool cut_index_present

Cut Index present bit.

Bits: [28:28]

bool vs_data_addr_present

VS Data Addr present bit.

Bits: [27:27]

bool vs_other_present

VS info present bit.

Bits: [26:26]

bool ds_present

DS info present bit.

Bits: [24:24]

bool gs_present

GS info present bit.

Bits: [23:23]

bool hs_present

HS info present bit.

Bits: [22:22]

uint32_t cam_size

Applies to DS if enabled, otherwise VS.

Bits: [7:14]

enum ROGUE_VDMCTRL_UVS_SCRATCH_SIZE_SELECT uvs_scratch_size_select
  • Applies to whichever shader writes into the UVS. I.e., GS if enabled, else DS if enabled, else VS.

    In addition to VERTEX_OUTPUT_SIZE, the VDM will tell the PDS to allocate additional space in the UVS based on the setting of this field. If rasterisation is enabled, UVS_SCRATCH_SIZE_SELECT should be set to 5 DWords. If only streaming out to memory, 1 DWord is sufficient. When 1, allocate an extra 1 DWords. When 0, allocate an extra 5 DWords.

  • Bits: [6:6]

bool cut_index_enable

Enable cut index.

Bits: [5:5]

bool tess_enable

Tessellation (DS + HS) enable.

Bits: [4:4]

bool gs_enable

Geometry shader enable.

Bits: [3:3]

enum ROGUE_VDMCTRL_FLATSHADE_CONTROL flatshade_control

Flat shade colour source.

Bits: [1:2]

bool generate_primitive_id

PrimID generate enable.

Bits: [0:0]

ROGUE_VDMCTRL_VDM_STATE1_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE1

ROGUE_VDMCTRL_VDM_STATE2_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE2

ROGUE_VDMCTRL_VDM_STATE3_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE3

ROGUE_VDMCTRL_VDM_STATE4_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE4

ROGUE_VDMCTRL_VDM_STATE5_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_VDM_STATE5

ROGUE_VDMCTRL_INDEX_LIST0_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST0

struct ROGUE_VDMCTRL_INDEX_LIST0

Index List word 0.

enum ROGUE_VDMCTRL_BLOCK_TYPE block_type

Index List.

Bits: [29:31] Default: INDEX_LIST

bool index_addr_present

Present bit for word 1.

Bits: [28:28]

bool index_count_present

Present bit for word 2.

Bits: [27:27]

bool index_instance_count_present

Present bit for word 3.

Bits: [26:26]

bool index_offset_present

Present bit for word 4.

Bits: [25:25]

bool start_present

Present bit for word 5 & 6.

Bits: [24:24]

bool indirect_addr_present

Present bit for words 7 & 8.

Bits: [23:23]

bool split_count_present

Present bit for word 9.

Bits: [22:22]

bool degen_cull_enable

Enable Degenerate Culling in VDM.

Bits: [19:19]

enum ROGUE_VDMCTRL_INDEX_SIZE index_size

8-bit (0), 16-bit (1) or 32-bit (2) indices.

Bits: [17:18]

uint32_t patch_count

Number of indices in a patch. (0=1, 1=2, … ).

Bits: [12:16]

enum ROGUE_VDMCTRL_PRIMITIVE_TOPOLOGY primitive_topology

The primitive topology.

Bits: [8:11]

uint64_t index_base_addrmsb

MSB of index buffer address.

Bits: [0:7]

ROGUE_VDMCTRL_INDEX_LIST1_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST1

ROGUE_VDMCTRL_INDEX_LIST2_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST2

ROGUE_VDMCTRL_INDEX_LIST3_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST3

ROGUE_VDMCTRL_INDEX_LIST4_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST4

ROGUE_VDMCTRL_INDEX_LIST5_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST5

ROGUE_VDMCTRL_INDEX_LIST6_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST6

ROGUE_VDMCTRL_INDEX_LIST7_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST7

ROGUE_VDMCTRL_INDEX_LIST8_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST8

ROGUE_VDMCTRL_INDEX_LIST9_length

Number of 32-bit words used to encode ROGUE_VDMCTRL_INDEX_LIST9

Implementation

The generator is implemented in Python and located at src/imagination/csbgen/gen_pack_header.py. XML specifications are located in src/imagination/csbgen/rogue/.